參數資料
型號: GS816236B-133IT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 512K X 36 CACHE SRAM, 8.5 ns, PBGA119
封裝: FBGA-119
文件頁數: 38/38頁
文件大?。?/td> 1609K
代理商: GS816236B-133IT
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Single/Dual Cycle Deselect Control
SCD
L
Dual Cycle Deselect
H or NC
Single Cycle Deselect
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
9th Bit Enable
PE
L
Activate DQPx I/Os (x18/x36 mode)
H or NC
Deactivate DQPx I/Os (x16/x32 mode)
GS816218(B/D)/GS816236(B/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.18 11/2005
9/38
1999, GSI Technology
Note:
There are pull-up devices on the ZQ, SCD, and FT pinsand a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
BPR 1999.05.18
相關PDF資料
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GS8162Z72AC-300 256K X 72 ZBT SRAM, 5 ns, PBGA209
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