
Rev:  1.01  11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
1/24
 2000, Giga Semiconductor, Inc.
Preliminary
GS8150Z18/36T-225/200/180/166/150/133
16Mb Pipelined and Flow Through 
Synchronous NBT SRAM
225 MHz
–
133 MHz
3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
 User-configurable Pipeline and Flow Through mode
 NBT (No Bus Turn Around) functionality allows zero wait 
read-write-read bus utilization; Fully pin-compatible with 
both pipelined and flow through NtRAM, NoBL and 
ZBT SRAMs
 3.3 V +10%/
–
5% core power supply
 2.5 V or 3.3 V I/O supply
 LBO pin for Linear or Interleave Burst mode
 Pin compatible with 2M, 4M, and 8M devices
 Byte write operation (9-bit Bytes)
 3 chip enable signals for easy depth expansion
 ZZ Pin for automatic power-down
 JEDEC-standard 100-lead TQFP  package
-225 -200 -180 -166 -150 -133 Unit
Pipeline
3-1-1-1
tCycle
Curr (x18)
Curr (x36)
410
370
Flow 
Through
2-1-1-1
Curr (x18)
Curr (x36)
240
210
Functional Description
The GS8150Z18/36T is a 16Mbit Synchronous Static SRAM. 
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other 
pipelined read/double late write or flow through read/single 
late write SRAMs, allow utilization of all available bus 
bandwidth by eliminating the need to insert deselect cycles 
when the device is switched from read to write cycles. 
Because it is a synchronous device, address, data inputs, and 
read/ write control inputs are captured on the rising edge of the 
input clock. Burst order control (LBO) must be tied to a power 
rail for proper operation. Asynchronous inputs include the 
Sleep mode enable (ZZ) and Output Enable. Output Enable can 
be used to override the synchronous control of the output 
drivers and turn the RAM's output drivers off at any time. 
Write cycles are internally self-timed and initiated by the rising 
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs 
and simplifies input signal timing. 
The GS8150Z18/36T  may be configured by the user to operate 
in Pipeline or Flow Through mode. Operating as a pipelined 
synchronous device, meaning that in addition to the rising edge 
triggered registers that capture input signals, the device 
incorporates a rising-edge-triggered output register. For read 
cycles, pipelined SRAM output data is temporarily stored by 
the edge triggered output register during the access cycle and 
then released to the output drivers at the next rising edge of 
clock. 
The GS8150Z18/36T is implemented with GSI's high 
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package. 
t
KQ
2.5
4.4
350
3.0
5.0
315
3.2
5.5
290
340
8
10
185
210
3.5
6.0
270
315
8.5
10
185
210
3.8
6.6
250
290
10
10
185
210
4.0
7.5
230
260
11
15
140
160
ns
ns
mA
mA
ns
ns
mA
mA
t
KQ
tCycle
7.0
8.5
205
7.5
10
185
A
B
C
D
E
F
R
W
R
W
R
W
Q
A
D
B
Q
C
D
D
Q
E
Q
A
D
B
Q
C
D
D
Q
E
Clock
Address
Read/Write
Flow Through
Data I/O
Pipelined
Data I/O
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles