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參數(shù)資料
| 型號： | GS8151E18 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（1M x 18Bit) Sync Burst SRAM(16M位（1M x 18位)同步靜態(tài)RAM（帶2位脈沖地址計數(shù)器）) |
| 中文描述： | 16Mb的（100萬x 18位）同步突發(fā)靜態(tài)存儲器（1,600位（100萬× 18位）同步靜態(tài)隨機(jī)存儲器（帶2位脈沖地址計數(shù)器）） |
| 文件頁數(shù)： | 1/31頁 |
| 文件大?。?/td> | 578K |
| 代理商： | GS8151E18 |
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Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
1/31
1999, Giga Semiconductor, Inc.
Preliminary
GS8151E18/36T-225/200/180/166/150/133
1M x 18, 512K x 36
16Mb Sync Burst SRAMs
225 MHz
–
133 MHz
3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
FT pin for user-configurable flow through or pipeline opera-
tion
Dual Cycle Deselect (DCD) operation
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip read parity checking; even or odd selectable
3.3 V +10%/
–
5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS8151E18/36T is a 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8151E18/36T is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
ByteSafe Parity Functions
The GS8151E18/36 features ByteSafe data security functions.
See detailed discussion following.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8151E18/36T operates on a 3.3 V power supply. All
input are 3.3 V- and 2.5 V-compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the
internal circuits and are 3.3 V- and 2.5 V-compatible.
-225 -200 -180 -166 -150 -133 Unit
4.4
2.5
205
240
210
210
210
7.0
8.5
350
410
370
340
315
Flow
Through
2-1-1-1
tCycle
t
KQ
Curr (x18)
Curr (x36)
t
KQ
tCycle
Curr (x18)
Curr (x36)
5.0
3.0
185
5.5
3.2
185
6.0
3.5
185
6.6
3.8
185
210
10.0
10.0
250
290
7.5
4.0
140
160
11.0
15.0
230
260
ns
ns
mA
mA
ns
ns
mA
mA
Pipeline
3-1-1-1
7.5
10.0
315
8.0
10.0
290
8.5
10.0
270
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