參數(shù)資料
型號(hào)： GS81302QT07E-333
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 16M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件頁(yè)數(shù)： 30/30頁(yè)
文件大?。?/td> 914K
代理商： GS81302QT07E-333
GS81302QT07/10/19/37E-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 5/2011
9/30
2011, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175
Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaQuad-II+ SRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock (K,K)
input receivers. The input termination is always enabled, and the impedance is programmed via the same RQ resistor (connected
between the ZQ pin and VSS) used to program output driver impedance, in conjuction with the ODT pin (6R). When the ODT pin
is tied Low, input termination is "strong" (i.e., low impedance), and is nominally equal to RQ*0.3 Thevenin-equivalent when RQ is
between 175 and 350. When the ODT pin is tied High (or left floating—the pin has a small pull-up resistor), input termination
is "weak" (i.e., high impedance), and is nominally equal to RQ*0.6 Thevenin-equivalent when RQ is between 175 and 250.
Periodic readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same
manner as for driver impedance (see above).
Note:
D, BW, K, K inputs should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are
tri-stated, the input termination will pull the signal to VDDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause
the receiver to enter a meta-stable state, resulting in the receiver consuming more power than it normally would. This could result
in the device’s operating currents being higher.
相關(guān)PDF資料
PDF描述
GS81302TT07E-333IT 16M X 8 DDR SRAM, 0.45 ns, PBGA165
GS81302TT07GE-333I 16M X 8 DDR SRAM, 0.45 ns, PBGA165
GS816036AGT-250I 512K X 36 CACHE SRAM, 5.5 ns, PQFP100
GS8160E36GT-250 512K X 36 CACHE SRAM, 5.5 ns, PQFP100
GS816118AGT-200IT 1M X 18 CACHE SRAM, 6.5 ns, PQFP100
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