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參數(shù)資料
| 型號： | GS81302QT07E-333 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 16M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數(shù)： | 28/30頁 |
| 文件大小： | 914K |
| 代理商： | GS81302QT07E-333 |
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GS81302QT07/10/19/37E-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 5/2011
7/30
2011, GSI Technology
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
Alternating Read-Write Operations
SigmaQuad-II+ SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for
details.
SigmaQuad-II B2 SRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,
begins a read cycle. Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.
SigmaQuad-II B2 SRAM DDR Write
The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of
K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is
clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on
the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NWx” may be substituted in all the discussion above.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS81302TT07E-333IT | 16M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| GS81302TT07GE-333I | 16M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| GS816036AGT-250I | 512K X 36 CACHE SRAM, 5.5 ns, PQFP100 |
| GS8160E36GT-250 | 512K X 36 CACHE SRAM, 5.5 ns, PQFP100 |
| GS816118AGT-200IT | 1M X 18 CACHE SRAM, 6.5 ns, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| GS81302S18E-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.5NS 165FPBGA - Trays |
| GS81302S18E-167I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.5NS 165FPBGA - Trays |
| GS81302S18E-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.45NS 165FPBGA - Trays |
| GS81302S18E-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.45NS 165FPBGA - Trays |
| GS81302S18E-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.45NS 165FPBGA - Trays |
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