參數(shù)資料
型號: GS71024U-9
廠商: Electronic Theatre Controls, Inc.
英文描述: 64K x 24 1.5Mb Asynchronous SRAM
中文描述: 64K的× 24即:1.5MB異步SRAM
文件頁數(shù): 13/13頁
文件大?。?/td> 278K
代理商: GS71024U-9
GS71024T/U
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 11/2004
9/13
1999, GSI Technology
Write Cycle 1: WE control
Write Cycle 2: CE control
tWC
Address
CE1(*1)
V/S
WE
Data In
OE
Data Out
tAW
tCW
tVW
tAS
tWP
tWR
tDW
tDH
tWLZ
tWHZ
Data valid
High impedance
(*2)
(*3)
tVS
*1 CE1 represents both CE1 low and CE2 high.
*2 Write is executed when both CE1 and WE are at low simultaneously.
*3 Do not apply the data input voltage to the output while DQ pin is in output condition.
tWC
Address
CE1(*1)
V/S
WE
Data In
OE
Data Out
tAW
tWP
tAS
tCW
tWR1
tDW
tDH
Data valid
High impedance
tVW
*1 CE1 represents both CE1 low and CE2 high.
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