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參數(shù)資料
| 型號： | GS71024U-9I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 64K x 24 1.5Mb Asynchronous SRAM |
| 中文描述： | 64K的× 24即：1.5MB異步SRAM |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 278K |
| 代理商： | GS71024U-9I |
GS71024T/U
64K x 24
1.5Mb Asynchronous SRAM
8, 9, 10, 12, 15 ns
3.3 V VDD
Center VDD and VSS
TQFP, FP-BGA
Commercial Temp
Industrial Temp
Rev: 1.05 11/2004
1/13
1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
Fast access time: 8, 9, 10, 12, 15 ns
CMOS low power operation: 190/170/160/130/110 mA at
minimum cycle time.
Single 3.3 V ± 0.3 V power supply
All inputs and outputs are TTL-compatible
Fully static operation
Industrial Temperature Option: –40 to 85°C
Package
T: 100-pin TQFP package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array
GT: Pb-Free 100-pin TQFP available
Description
The GS71024 is a high speed CMOS static RAM organized as
65,536 words by 24 bits. Static design eliminates the need for
external clocks or timing strobes. The GS71024 operates on a
single 3.3 V power supply, and all inputs and outputs are TTL-
compatible. The GS71024 is available in a 6 mm x 8 mm Fine
Pitch BGA package, as well as in a 100-pin TQFP package.
Fine Pitch BGA Bump Configuration
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Block Diagram
1
234
56
A
DQ
A3
A2
A1
A0
DQ
B
DQ
CE2 WE
DQ
C
DQ
CE1
OE
DQ
D
VSS DQ
A5
A4
DQ
VDD
E
VDD DQ
A7
A6
DQ
VSS
F
DQ
A9
A8
DQ
G
DQ
A11
A10
DQ
H
DQ
A15
A14
A13
A12
DQ
Pin Descriptions
Symbol
Description
Symbol
Description
A0 to A15
Address input
DQ1 to DQ24
Data input/output
X/Y
Vector Input
V/S
Address Multiplexer Control
WE
Write enable input
OE
Output enable input
CE1, CE2
Chip enable input
—
VDD
+3.3 V power supply
VSS
Ground
Memory Array
1024 x 1536
Row
Decoder
Column
Decoder
Address
Input
Control
I/O Buffer
A0
A15
CE1
WE
OE
DQ1
DQ24
0
1
Q
A14
X/Y
V/S
CE2
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