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參數(shù)資料
| 型號(hào)： | GS7000 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Serial Digital Video Transceiver |
| 中文描述： | 串行數(shù)字視頻收發(fā)器 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 172K |
| 代理商： | GS7000 |
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2
G
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
Supply Voltage
5.5V
Input Voltage Range (any input)
V
EE
< V
IN
< V
CC
DC Input Current (any one input)
10mA
Power Dissipation (V
CC
= 5.25 V)
830mW
Maximum Die Temperature
125°C
Operating Temperature Range
0°C
≤
T
A
≤
85°C
Storage Temperature Range
-65°C
≤
T
S
≤
150°C
Lead Temperature (soldering 10s)
260°C
AC ELECTRICAL CHARACTERISTICS (Receiver Mode)
V
= 5V, V
= 0V, T
= 0°C to 85°C, unless otherwise specified.
Serial Data Rate = 270Mb/s, Parallel Data Rate = 27Mb/s, f
PCLK
= 27MHz
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
TEST
LEVEL
Parallel Data Output - Rise/Fall Time
C
L
= 20pF
t
R/F_PDO
1.0
-
6.0
ns
1
1
PCLK rising edge to D
OUT(n)
center
t
D
-
-
± 5
ns
2, 3
1
PCLK rise/fall time
C
L
= 20pF
t
R/F_PCLKo
0.5
-
3.0
ns
1
1
Input Return Loss
75
match
5MHz -> 270MHz
LOSS
IN
-
17
-
dB
6
Asynchronous Lock Time
t
LOCK_ASYNC
-
-
250
ms
4
1
Synchronous Lock Time
t
LOCK_SYNC
-
-
10
μs
5
1
Input Jitter Tolerance
pathological Input
t
J_SI
-
0.4
-
U.I.
6
4
Output PCLK Jitter
pathological Input
t
J_PCLKo
-
1000
-
ps p-p
6
1
Max Error Free Cable Length
pathological Input
75
100
-
m
6, 7
1, 4
NOTES
1. Rise/Fall time is defined as the time for the signal to rise from 20% to 80% of the specified p-p value,
or to fall from 80% to 20% of the specified value.
2. Refer also to Figure 21.
3. This is the time difference between the rising edge of PCLK
OUT
and the center of the bit period.
4. This is the time delay between a valid serial TRS signal on the input, to the moment valid data
appears on the parallel outputs.
5. This is the time for the PLL to re-lock when video streams are switched during the vertical blanking
interval in accordance with SMPTE RP168-1993. The two streams may be 180° out of phase with
respect to one another, but pixel aligned.
6. This pathological pattern is defined in SMPTE RP178-1996, paragraphs 4.1 and 4.3.
7. "Error free" is defined as no single bit errors over a period of 10 minutes, using Belden 8281 Cable
and 75
connections. The MIN value is fully tested and the TYP value is based on using the
EB7000 Evaluation Board.
TEST LEVELS
1. 100% tested at 25 °C
2. Guaranteed by design
3. Inferred or correlated
value
4. Evaluated using test
setup Figure 1a.
5. Evaluated using test
setup Figure 1b.
6. Evaluated using test
setup Figure 1c.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS7000-CQT | Serial Digital Video Transceiver |
| GS7000-CTT | Serial Digital Video Transceiver |
| GS7005 | Complete Serial Digital Video Receiver |
| GS7005-CQT | Complete Serial Digital Video Receiver |
| GS7005-CTT | Complete Serial Digital Video Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS7000-CQT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Video Transceiver |
| GS7000-CTT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Video Transceiver |
| GS7005 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Complete Serial Digital Video Receiver |
| GS7005CQT | 制造商:Gennum Corporation 功能描述: |
| GS7005-CQT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Complete Serial Digital Video Receiver |
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