參數(shù)資料
型號(hào): GS7000
廠商: Electronic Theatre Controls, Inc.
英文描述: Serial Digital Video Transceiver
中文描述: 串行數(shù)字視頻收發(fā)器
文件頁(yè)數(shù): 11/14頁(yè)
文件大小: 172K
代理商: GS7000
522 - 06 - 02
11
G
The figure below describes the relationship between the input parallel clock and the input parallel data. The input parallel
data must be stable for 4ns prior to the rising edge of the PCLK
IN
(setup time), and for 4 ns following the rising edge of the
PCLK
IN
(hold time).
Fig. 22 Transmitter Setup and Hold Time
TYPICAL APPLICATION CIRCUITS
Typical Receiver Application Circuit with External Equalizer
t
HOLD
= 4ns
t
SETUP
= 4ns
D
IN(n)
PCLK
IN
27 28 29 30 31 32 33 34 35 36 37 38 39
GS7000
N
H
D
I
D
I
D
I
D
I
D
I
D
I
D
I
D
I
D
I
D
I
N
N
L
D
O
D
O
D
O
D
O
D
O
D
O
D
O
D
O
D
O
D
O
N
NC
V
EE3
SDO
SDO
V
CC3
CD
SMPTE
NC
NC
PCLK
OUT
V
DD
V
SS
NC
NC
V
EE1
C
1
C
2
V
CC1
SDI
SDI
V
CC2
PCLK
IN
V
EE2
EQ
Rx/Tx
NC
V
CC
V
CC
220
100n
V
CC
V
CC
220
10k
MODE
100n
100n
LOCK
CD
100n
475
V
CC
PARALLEL DATA OUTPUTS
V
CC
75
75
100n
10k
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
V
CC
33
10p
PCLK OUT
V
CC
AGC
GND
V
CC
D
IN
D
IN
GND
V
CC
AGC
TRISTATE
CD
D
OUT
D
OUT
CD-ADJ
OEM
GS9024
V
CC
10n
100p
V
CC
V
CC
V
CC
V
CC
10n
10n
75
75
75
37.5
10n
10n
1u
75
10n
10n
475
2k
100n
10u
V
CC1
GND
SSI-CD
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
13 12 11 10
9 8
7
6
5
4
3
2
1
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