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參數(shù)資料
| 型號： | GMZAN3T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA ALALOG INTERFACE LCD MONITOR CONTROLLER |
| 中文描述： | ALALOG的XGA液晶顯示器接口控制器 |
| 文件頁數(shù)： | 16/53頁 |
| 文件大?。?/td> | 556K |
| 代理商： | GMZAN3T |
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gmZAN3 Preliminary Data Sheet
C0523-DAT-01G
23
July 2003
Ge nes i s Microc hip Confid e n tia l
http:// w ww . g enesis-mic r ochip.com
Maximum Duty Cycle
40-60
4.1.3 Clock Synthesis
The gmZAN3 synthesizes all additional clocks internally as illustrated in Figure 9 below. The synthesized
clocks are as follows:
1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is derived from
the TCLK/XTAL pad input.
2. Reference Clock (RCLK) synthesized by RCLK PLL (RPLL) using TCLK as the reference.
3. Input Source Clock (SCLK) synthesized by Source DDS (SDDS) PLL using input HSYNC as the
reference. The SDDS internal digital logic is driven by RCLK.
4. ADC Output Clock (ACLK) is a delay-adjusted ADC sampling clock, ACLK. ACLK is derived from
SCLK.
5. Host Port Clock for OSD SRAM and muxed A/D port. TCLK at power up, and selectable as RCLK/2
or RCLK/4.
SDDS
DDDS
ACLK
DCLK
HSYNC
SCLK
TCLK
M
U
X
÷2
RCLK
PLL
HOST_CLK
for muxed A/D
8051 interface
÷4
Figure 9.
Internally Synthesized Clocks
The on-chip clock domains are selected from the synthesized clocks. These include:
1. ADC Domain Clock (ACLK) which is also the input clock. Max = 100MHz
2. Host Interface (HOST_CLK). Max = 120MHz
3. Scaler and Display Pixel Clock (DP_CLK). Max = 100MHz
4. Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz
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