gmZAN3 Preliminary Data Sheet
C0523-DAT-01G
19
July 2003
Ge nes i s Microc hip Confid e n tia l
http:// w ww . g enesis-mic r ochip.com
4 Functional Description
A functional block diagram is illustrated below. Each of the functional units shown is described in the
following sections.
GPIO
Host I/F
gmZAN3L
Single Channel
LVDS Panel Data
and Control
Analog
RGB
Triple
ADC
& PLL
Image
Capture /
Measure-
ment
Zoom /
Shrink /
Filter
Crystal
Reference
Clock
Generation
OSD
Controller
OSD
RAMs
Gamma
Control
Host
Interface
Output
Data
Path
LVDS
Transmitter
Reset
Circuit
Energy
Spectrum
Manager
HS, VS
24/36/48-bit
TTL Output
Test
Pattern
Generator
gmZAN3T
TTL output to LCD
Panel
Figure 4.
gmZAN3 Functional Block Diagram
4.1 Clock Generation
The gmZAN3 features two clock inputs. All additional clocks are internal clocks derived from one or
more of these:
1. Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator and
corresponding logic. A 14.318 MHz crystal is recommended. Other crystal frequencies may be used,
but require custom programming. This is illustrated in
Figure 5 below. This option is selected by
connecting a 10K
pull-up to HDATA2/AD2/OSC_SEL. Alternatively a single-ended TTL/CMOS
clock oscillator can be driven into the TCLK pin (leave XTAL and HDATA2/AD2/OSC_SEL as N/C
2. Host Interface Transfer Clock (HCLK). For 2 or 6-wire Host Interface Port only. Not for muxed A/D.
The gmZAN3 TCLK oscillator circuitry is a custom designed circuit to support the use of an external
oscillator or a crystal resonator to generate a reference frequency source for the gmZAN3 device.
4.1.1 Using the Internal Oscillator with External Crystal
The first option for providing a clock reference is to use the internal oscillator with an external crystal.
The oscillator circuit is designed to provide a very low jitter and very low harmonic clock to the internal
circuitry of the gmZAN3. An Automatic Gain Control (AGC) is used to insure startup and operation over