參數(shù)資料
型號： GMS81C5032-XXXSK
英文描述： MICROCONTROLLER|8-BIT|CMOS|DIP|28PIN|PLASTIC
中文描述： 單片機(jī)| 8位|的CMOS |雙酯| 28腳|塑料
文件頁數(shù)： 66/93頁
文件大小： 853K
代理商： GMS81C5032-XXXSK
GMS81C1404/GMS81C1408
64
June. 2001 Ver 1.2
18. WATCHDOG TIMER
The purpose of the watchdog timer is to detect the mal-
function (runaway) of program due to external noise or
other causes and return the operation to the normal condi-
tion.
The watchdog timer has two types of clock source.
The first type is an on-chip RC oscillator which does not
require any external components. This RC oscillator is sep-
arate from the external oscillator of the Xin pin. It means
that the watchdog timer will run, even if the clock on the
Xin pin of the device has been stopped, for example, by en-
tering the STOP mode.
The other type is a prescaled system clock.
The watchdog timer consists of 7-bit binary counter and
the watchdog timer data register. When the value of 7-bit
binary counter is equal to the lower 7 bits of WDTR, the
interrupt request flag is generated. This can be used as
WDT interrupt or reset the CPU in accordance with the bit
WDTON.
Note:
Because the watchdog timer counter is enabled af-
ter clearing Basic Interval Timer, after the bit WD-
TON set to “1”, maximum error of timer is depend on
prescaler ratio of Basic Interval Timer.
The 7-bit binary counter is cleared by setting WDTCL(bit7
of WDTR) and the WDTCL is cleared automatically after
1 machine cycle.
The RC oscillated watchdog timer is activated by setting
the bit RCWDT as shown below.
The RC oscillation period is vary with temperature, V
DD
and process variations from part to part (approximately,
40~120uS). The following equation shows the RC oscillat-
ed watchdog timer time-out.
T
RCWDT
=CLK
RC
×2
8
×[
WDTR.6~0]+(CLK
RC
×2
8
)/2
where, CLK
RC
= 40~120uS
In addition, this watchdog timer can be used as a simple 7-
bit timer by interrupt WDTIF. The interval of watchdog
timer interrupt is decided by Basic Interval Timer. Interval
equation is as below.
T
WDT
= [WDTR.6~0]
×
Interval of BIT
Figure 18-1 Block Diagram of Watchdog Timer
:
LDM
LDM
STOP
NOP
NOP
:
CKCTLR,#3FH
WDTR,#0FFH
; enable the RC-osc WDT
; set the WDT period
; enter the STOP mode
; RC-osc WDT running
÷
8
÷
16
÷
32
÷
64
÷
128
÷
256
÷
512
÷
1024
0
1
MUX
8
3
fxin
BITR (8-bit)
BTS[2:0]
RCWDT
Internal RC OSC
Basic Interval Timer
Interrupt
BTCL
Clear
Watchdog Timer
Interrupt Request
BITIF
7-bit Counter
WDTR (8-bit)
OFD
WDTCL
WDTON
CPU RESET
1
0
Clock Control Register
CKCTLR
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
-
WAKEUP RCWDT
WDTON
BTCL
BTS2
BTS1
BTS0
-
0
X
1
X
X
X
X
Watchdog Timer Register
WDTR
ADDRESS : EDH
RESET VALUE : 01111111
Bit Manipulation Not Available
WDTCL
7-bit Watchdog Counter Register
Overflow Detection
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