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參數(shù)資料
| 型號(hào)： | GMS81C5032-XXXSK |
| 英文描述： | MICROCONTROLLER|8-BIT|CMOS|DIP|28PIN|PLASTIC |
| 中文描述： | 單片機(jī)| 8位|的CMOS |雙酯| 28腳|塑料 |
| 文件頁(yè)數(shù)： | 30/93頁(yè) |
| 文件大?。?/td> | 853K |
| 代理商： | GMS81C5032-XXXSK |
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GMS81C1404/GMS81C1408
28
June. 2001 Ver 1.2
Note:
Several names are given at same address. Refer to
below table.
Stack Area
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the pro-
gram counter and flags.
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save.
1. “byte, bit” means that register can be addressed by not only bit
but byte manipulation instruction.
2. “byte” means that register can be addressed by only byte
manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for
clearing bit.
Addr.
When read
When write
Timer
Mode
Capture
Mode
PWM
Mode
Timer
Mode
PWM
Mode
D1H
T0
CDR0
-
TDR0
-
D3H
-
TDR1
T1PPR
D4H
T1
CDR1
T1PDR
-
T1PDR
D7H
T2
CDR2
-
TDR2
-
D9H
-
TDR3
T3PPR
DAH
T3
CDR3
T3PDR
-
T3PDR
ECH
BITR
CKCTLR
Table 9-2 Various Register Name in Same Address
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