參數(shù)資料
型號(hào)： GMS81C5032-XXXPL
英文描述： MICROCONTROLLER|8-BIT|CMOS|LDCC|44PIN|PLASTIC
中文描述： 單片機(jī)| 8位|的CMOS | LDCC | 44PIN |塑料
文件頁(yè)數(shù)： 60/93頁(yè)
文件大小： 853K
代理商： GMS81C5032-XXXPL
GMS81C1404/GMS81C1408
58
June. 2001 Ver 1.2
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IENH, IENL) and the interrupt request flags (in IRQH,
IRQL) except Power-on reset and software BRK interrupt.
Interrupt enable registers are shown in Figure 17-2 . These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determines whether an interrupt
will be accepted or not. When enable flag is “0”, a corre-
sponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once.
Figure 17-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occurred, the I-flag is cleared and dis-
able any further interrupt, the return address and PSW are
pushed into the stack and the PC is vectored to. Once in the
interrupt service routine the source(s) of the interrupt can
be determined by polling the interrupt request flag bits.
The interrupt request flag bit(s) must be cleared by soft-
ware before re-enabling interrupts to avoid recursive inter-
rupts. The Interrupt Request flags are able to be read and
written.
Reset/Interrupt
Symbol
Priority
Vector Addr.
Hardware Reset
External Interrupt 0
External Interrupt 1
Timer 0
Timer 1
External Interrupt 2
External Interrupt 3
Timer 2
Timer 3
A/D Converter
Watch Dog Timer
Basic Interval Timer
Serial Interface
RESET
INT0
INT1
Timer 0
Timer 1
INT2
INT3
Timer 2
Timer 3
A/D C
WDT
BIT
SPI
-
1
2
3
4
5
6
7
8
9
10
11
12
FFFE
H
FFFA
H
FFF8
H
FFF6
H
FFF4
H
FFF2
H
FFF0
H
FFEE
H
FFEC
H
FFEA
H
FFE8
H
FFE6
H
Table 17-1 Interrupt Priority
IENH
ADDRESS : E2H
RESET VALUE : 00000000
INT0E
INT1E
T0E
T1E
INT2E
INT3E
T2E
T3E
Interrupt Enable Register High
IENL
ADDRESS : E3H
RESET VALUE : 0000----
ADE
WDTE
BITE
SPIE
-
-
-
-
Interrupt Enable Register Low
IRQH
ADDRESS : E4H
RESET VALUE : 00000000
INT0IF
INT1IF
T0IF
T1IF
INT2IF
INT3IF
T2IF
T3IF
Interrupt Request Register High
IRQL
ADDRESS : E5H
RESET VALUE : 0000----
ADIF
WDTIF
BITIF
SPIF
-
-
-
-
Interrupt Request Register Low
0 : Disable
1 : Enable
Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.
0 : Not occurred
1 : Interrupt request is occurred
Shows the interrupt occurrence
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