參數(shù)資料
型號: GMS81C5024-XXXPLT
英文描述: MICROCONTROLLER|8-BIT|CMOS|LDCC|44PIN|PLASTIC
中文描述: 單片機(jī)| 8位|的CMOS | LDCC | 44PIN |塑料
文件頁數(shù): 32/93頁
文件大?。?/td> 853K
代理商: GMS81C5024-XXXPLT
GMS81C1404/GMS81C1408
30
June. 2001 Ver 1.2
EAH
ADCM
-
-
ADEN
ADS2
ADS1
ADS0
ADST
ADSF
EBH
ADCR
ADC Result Data Register
ECH
BITR
1
Basic Interval Timer Data Register
ECH
CKCTLR
1
-
WAKEUP
RCWDT
WDTON
BTCL
BTS2
BTS1
BTS0
EDH
WDTR
WDTCL
7-bit Watchdog Counter Register
EFH
PFDR
2
-
-
-
-
-
PFDIS
PFDM
PFDS
1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.
2.The register PFDR only be implemented on devices, not on In-circuit Emulator.
Table 9-3 Control Registers of GMS81C1404 and GMS81C1408
These registers of shaded area can not be accessed by bit manipulation instruction as “SET1, CLR1”, but should be accessed by
register operation instruction as “LDM dp,#imm”.
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