參數(shù)資料
型號(hào)： GMS81C5024-XXXPLT
英文描述： MICROCONTROLLER|8-BIT|CMOS|LDCC|44PIN|PLASTIC
中文描述： 單片機(jī)| 8位|的CMOS | LDCC | 44PIN |塑料
文件頁數(shù)： 29/93頁
文件大小： 853K
代理商： GMS81C5024-XXXPLT
GMS81C1404/GMS81C1408
June. 2001 Ver 1.2
27
9.3 Data Memory
Figure 9-7 shows the internal Data Memory space availa-
ble. Data Memory is divided into two groups, a user RAM
(including Stack) and control registers.
Figure 9-7 Data Memory Map
User Memory
The GMS81C1404 and GMS81C1408 has 192
×
8 bits for
the user memory (RAM).
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0
H
to 0FF
H
.
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.
More detailed informations of each register are explained
in each peripheral section.
Note:
Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write
instruction. Use byte manipulation instruction.
Example; To write at CKCTLR
LDM
CKCTLR,#09H ;Divide ratio
÷
16
USER
MEMORY
(including STACK)
CONTROL
REGISTERS
0000H
00BFH
00C0H
00FFH
PAGE0
Address
Symbol
R/W
RESET
Value
Addressing
mode
0C0H
0C1H
0C2H
0C3H
0C4H
0C5H
0C6H
0C7H
0CAH
0CBH
0CCH
0CDH
RA
RAIO
RB
RBIO
RC
RCIO
RD
RDIO
RAFUNC
RBFUNC
PUPSEL
RDFUNC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
Undefined
0000_0000
Undefined
00000000
Undefined
-000_0---
Undefined
----_-000
0000_0000
0000_0000
----_0000
----_--00
byte, bit
1
byte
2
byte, bit
byte
byte, bit
byte
byte, bit
byte
byte
byte
byte
byte
0D0H
0D1H
0D1H
0D1H
0D2H
0D3H
0D3H
0D4H
0D4H
0D4H
0D5H
TM0
T0
TDR0
CDR0
TM1
TDR1
T1PPR
T1
CDR1
T1PDR
PWM0HR
R/W
R
W
R
R/W
W
W
R
R
R/W
W
--00_0000
0000_0000
1111_1111
0000_0000
0000_0000
1111_1111
1111_1111
0000_0000
0000_0000
0000_0000
----_0000
byte, bit
byte
byte
byte
byte, bit
byte
byte
byte
byte
byte, bit
byte
0D6H
0D7H
0D7H
0D7H
0D8H
0D9H
0D9H
0DAH
0DAH
0DAH
0DBH
TM2
T2
TDR2
CDR2
TM3
TDR3
T3PPR
T3
CDR3
T3PDR
PWM1HR
R/W
R
W
R
R/W
W
W
R
R
R/W
W
--00_0000
0000_0000
1111_1111
0000_0000
0000_0000
1111_1111
1111_1111
0000_0000
0000_0000
0000_0000
----_0000
byte, bit
byte
byte
byte
byte, bit
byte
byte
byte
byte
byte, bit
byte
0DEH
0E0H
0E1H
BUR
SIOM
SIOR
W
R/W
R/W
1111_1111
0000_0001
Undefined
byte
byte, bit
byte, bit
0E2H
0E3H
0E4H
0E5H
0E6H
0EAH
0EBH
0ECH
0ECH
0EDH
0EDH
0EFH
IENH
IENL
IRQH
IRQL
IEDS
ADCM
ADCR
BITR
CKCTLR
WDTR
WDTR
PFDR
R/W
R/W
R/W
R/W
R/W
R/W
R
R
W
R
W
R/W
0000_0000
0000_----
0000_0000
0000_----
0000_0000
--00_0001
Undefined
0000_0000
-001_0111
0000_0000
0111_1111
----_-100
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte
byte
byte
byte
byte
byte, bit
Table 9-1 Control Registers
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