參數(shù)資料
型號(hào)： GMS81C5016-XXXQT
英文描述： MICROCONTROLLER|8-BIT|CMOS|QFP|44PIN|PLASTIC
中文描述： 單片機(jī)| 8位|的CMOS | QFP封裝| 44PIN |塑料
文件頁數(shù)： 64/93頁
文件大?。?/td> 853K
代理商： GMS81C5016-XXXQT
GMS81C1404/GMS81C1408
62
June. 2001 Ver 1.2
17.4 External Interrupt
The external interrupt on INT0, INT1, INT2 and INT3 pins
are edge triggered depending on the edge selection register
IEDS (address 0E6
H
) as shown in Figure 17-6 .
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
Figure 17-6 External Interrupt Block Diagram
Example: To use as an INT0 and INT2
:
:
;
**** Set port as an input port RB2,RD0
LDM
LDM
;
;
**** Set port as an interrupt port
LDM
LDM
;
;
**** Set Falling-edge Detection
LDM
:
:
:
RBIO,#1111_1011B
RDIO,#1111_1110B
RBFUNC,#04H
RDFUNC,#01H
IEDS,#0001_0001B
Response Time
The INT0, INT1,INT2 and INT3 edge are latched into
INT0IF, INT1IF, INT2IF and INT3IF at every machine
cycle. The values are not actually polled by the circuitry
until the next machine cycle. If a request is active and con-
ditions are right for it to be acknowledged, a hardware sub-
routine call to the requested service routine will be the next
instruction to be executed. The DIV itself takes twelve cy-
cles. Thus, a minimum of twelve complete machine cycles
elapse between activation of an external interrupt request
and the beginning of execution of the first instruction of
the service routine.
INT0IF
INT0 pin
INT0 INTERRUPT
INT1IF
INT1 pin
INT1 INTERRUPT
INT2IF
INT2 pin
INT2 INTERRUPT
IEDS
[0E6
H
]
e
INT3IF
INT3 pin
INT3 INTERRUPT
INT0 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
Ext. Interrupt Edge Selection
Register
W
IESR
ADDRESS : 0E6
RESET VALUE : 00000000
W
W
W
00 : Int. disable
01 : falling
10 : rising
11 : both
W
W
W
INT1 edge select
INT3 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
W
INT2 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
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