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| 型號(hào)： | GMS81C2112Q |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | MQFP-44 |
| 文件頁數(shù)： | 62/93頁 |
| 文件大?。?/td> | 853K |
| 代理商： | GMS81C2112Q |
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GMS81C1404/GMS81C1408
60
June. 2001 Ver 1.2
The following method is used to save/restore the general-
purpose registers.
Example: Register save using push and pop instructions
General-purpose register save/restore using push and pop
instructions;
17.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.
Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distin-
guish BRK from TCALL 0.
Each processing step is determined by B-flag as shown in
Figure 17-4 .
Figure 17-4 Execution of BRK/TCALL0
17.3 Multi Interrupt
If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced.
However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further inter-
rupt can be serviced even if certain interrupt is in progress.
INTxx:
PUSH
PUSH
PUSH
A
X
Y
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
interrupt processing
POP
POP
POP
RETI
Y
X
A
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
main task
interrupt
service task
saving
registers
restoring
registers
acceptance of
interrupt
interrupt return
B-FLAG
BRK
INTERRUPT
ROUTINE
RETI
TCALL0
ROUTINE
RET
BRK or
TCALL0
=0
=1
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