參數(shù)資料
型號(hào)： GMS81C2112Q
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44
封裝： MQFP-44
文件頁(yè)數(shù)： 46/93頁(yè)
文件大小： 853K
代理商： GMS81C2112Q
GMS81C1404/GMS81C1408
44
June. 2001 Ver 1.2
These timers have each 8-bit count register and data regis-
ter. The count register is increased by every internal or ex-
ternal clock input. The internal clock has a prescaler divide
ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by con-
trol bits T0CK2, T0CK1 and T0CK0 of register TM0) and
1, 2, 8 (selected by control bits T1CK1 and T1CK0 of reg-
ister TM1). In the Timer 0, timer register T0 increases
from 00
H
until it matches TDR0 and then reset to 00
H
. The
match output of Timer 0 generates Timer 0 interrupt
(latched in T0F bit). As TDRx and Tx register are in same
address, when reading it as a Tx, written to TDRx.
In counter function, the counter is increased every 0-to 1
(rising edge) transition of EC0 pin. In order to use counter
function, the bit RA0 of the RA Direction Register RAIO
is set to “0”. The Timer 0 can be used as a counter by pin
EC0 input, but Timer 1 can not.
Figure 13-3 Counting Example of Timer Data Registers
Figure 13-4 Timer Count Operation
~
Timer 1 (T1IF)
Interrupt
TDR1
TIME
Occur interrupt
Occur interrupt
Occur interrupt
Interrupt period
= P
CP
x (n+1)
upcoun
~
~
0
1
2
3
4
5
6
7
8
9
n
n-1
P
CP
Timer 1 (T1IF)
Interrupt
TDR1
TIME
Occur interrupt
Occur interrupt
stop
clear & start
disable
enable
Start & Stop
T1ST
T1CN
Control count
upcoun
~
~
T1ST = 0
T1ST = 1
T1CN = 0
T1CN = 1
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