參數(shù)資料
型號(hào)： GMM7658287CNTG-5
英文描述： x64 EDO Page Mode DRAM Module
中文描述： X64的EDO公司頁(yè)面模式內(nèi)存模塊
文件頁(yè)數(shù)： 3/29頁(yè)
文件大?。?/td> 425K
代理商： GMM7658287CNTG-5
LG Semicon
GMM7654287CTG
Pin Description
Pin
Function
Pin
Function
A0-A11
DQ0-DQ63
V
CC
V
SS
NC
Address Inputs
Data Input/Output
Row Address Strobe
Column Address Strobe
Read/Write Enable
Power (+3.3V)
Ground
No Connection
RE0
CE0-CE7
WE
Serial Presence Detect Information
. SPD Interface Protocol : IIC
. Current sink capability of SDA driver
￡
= 3 mA
. Maximum Clock Frequency : 100 KHz
SDA
Serial Address / Data I/O
SCL
Serial Clock
SA0-SA2
Address in EEPROM
OE
Output Enable
RSVD
Reserved
* Above data are based on the SPD specification of JEDEC standard.
Byte
Function described
Function supported
0
1
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type(FPM, EDO..) form appendix A
# Row Address on this assembly
# Column Address on this assembly
256 bytes
EDO
12(4k refresh)
2
3
4
5
# Module Banks on this assembly
6
Data Width of this assembly
1(1 Banks)
64 bits
128 bytes
10
Module Data Width continuation
Voltage interface standard of this assembly
RAS # Access time of this assembly
CAS # Access time of this assembly
DIMM Configuration type(Non-Parity,Parity,ECC)
7
8
9
10
11
12
13
Refresh Rate/Type
DRAM Width, Primary DRAM
N/A
LVTTL
t
RAC
= 60 ns
4096/128ms
t
CAC
= 15 ns
Hex Value
80h
08h
0Ch
0Ah
02h
01h
40h
00h
01h
3Ch
0Fh
80h
00h
00h
x16
10h
14
Error checking DRAM data width
15-31
Reserved for future offerings
00h
32
Superset memory type(may be used in future)
00h
Non-Parity
RFU
Reserved for Future use
3
相關(guān)PDF資料
PDF描述
GMM7658287CNTG-6 x64 EDO Page Mode DRAM Module
GMM77316280CTG 16Mx72|3.3V|5/6|x 18|FP/EDO DRAM - 128MB Buffered DIMM
GMM77316280CTG-5 x72 EDO Page Mode DRAM Module
GMM77316280CTG-6 x72 EDO Page Mode DRAM Module
GMM77316380CTG 16Mx72|3.3V|5/6|x18|FP/EDO DRAM - 128MB Buffered DIMM
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