參數(shù)資料
型號: GLT5640L32-6
廠商: Electronic Theatre Controls, Inc.
英文描述: CMOS Synchronous DRAM 2M x 32 SDRAM
中文描述: 200萬的CMOS同步DRAM × 32內(nèi)存
文件頁數(shù): 27/72頁
文件大小: 2315K
代理商: GLT5640L32-6
G-LINK
GLT5640AL16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.0.1)
G-Link Technology Corporation, Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-27968078
- 27 -
10.2.2 Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command. The DQM must be high to mask invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid data
may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same
clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
CLK
Command
CAS latency = 2
DQM
Hi - Z
Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
RP
PRE
ACT
DQ
Write
PRE
ACT
t
RP
CASlatency = 3
Hi - Z
D0
D3
D2
D1
D0
D3
D2
D1
DQM
D4
D4
command
DQ
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