參數(shù)資料
型號: GJRF400
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP RF TRANSCEIVER
中文描述: 單芯片射頻收發(fā)器
文件頁數(shù): 6/8頁
文件大?。?/td> 117K
代理商: GJRF400
98-05
Gran Jansen Oslo Norway
6
Programming
A three line bus is used to program the circuit; the
three lines being: Data IXO, Clock and Load. Data
IXO is bi-directional and is used to transmit data,
receive data and to program the circuit. The 3-line
serial bus interface allows control over the frequency
dividers and the selective powering up of Tx, Rx and
Synthesiser circuit blocks.
The interface consists of a 59-bit programming register.
Data is entered on the Data IXO line with the most
significant bit first. The first bit entered is p1, the last one
p59. The bits in the programming register are arranged as
shown in table 5.
Table 5: Bit allocation
MSB Register bit allocation
p1 - p12
p13 - p24
p25 - p34
p35 - p44
p45
p46
N1
N0
M1
M0
BypassLNA
‘0’
Register bit allocation
p47
p48
p49
p50
p51
p52
p53
RxOutD
RxOutD_S
Fc0
Fc1
RecSel
RxOut
BiasS
Register bit allocation LSB
p54
p55
p56
p57
p58
p59
‘0’
GmBias
Mod1
Mod0
R_T
Pd
Table 6: Bit Description
N1
N0
M1
M0
BypassLNA
RxOutD
RxOutD_S
Fc0
Fc1
RecSel
frequency divider N1, 12 bits
frequency divider N0, 12 bits
frequency divider M1, 10 bits
frequency divider M0, 10 bits
1 = the LNA is bypassed
1 = the I or Q channel digital output is active on the RxOutD pin
Selects between the I (‘1’) and Q (‘0’) channel digital output
Bit to program the cut-off frequency of the RC filters
Bit to program the cut-off frequency of the RC filters
0 = the rectifier rectifies the output of the I-channel gyrator filter
1 = the rectifier rectifies the output of the I-channel passive RC filter
0 = the gyrator filter outputs are active on the IchOut and QchOut pins
1 = the RC filter outputs are active on the IchOut and QchOut pins
1 = the I and Q channel lowpass filter uses the same bias circuit, pin Vb_lp1
0 = the I and Q channel lowpass filter uses separate bias circuit,
pin Vb_lp1 (I) ,Vb_lp2 (Q)
1 = FSK frequency deviation > 30kHz 0 = FSK frequency deviation < 30kHz
Mod1 = 0, Mod0 = 0: No modulation
Mod1 = 0, Mod0 = 1: FSK modulation by switching between different dividers
Mod1 = 1, Mod0 = 0: FSK modulation can be applied to the VCO
Mod1 = 1, Mod0 = 1: FSK modulation can be applied to the crystal oscillator
0 = receive mode 1 = transmit mode
0 = power up 1 = power down
RxOut
BiasS
GmBias
Mod1
Mod0
R_T
Pd
When FSK modulation is applied to the VCO or to
the crystal oscillator the PLL is using the dividers N0
and M0. When Mod1 = 0 and Mod0 = 1 it is possible
to switch between the different dividers in the PLL.
The switching is controlled by Data IXO. When Data
IXO = 0 the PLL uses dividers N0 and M0. When Dat
IXO = 1 the PLL uses dividers N1 and M1. Switching
between the different dividers can be used to implement
low bitrate FSK modulation.
Example 3:
f
RF
= 433.92MHz, frequency deviation: ±40kHz, f
XCO
= 10.00MHz ( Modulation is applied to the VCO.)
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