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參數(shù)資料
| 型號(hào)： | GF9102ACPM |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ?,1X4 MALE HEADER,TH,+/-?% |
| 中文描述： | 元?dú)?內(nèi)插數(shù)字濾波器 |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大?。?/td> | 300K |
| 代理商： | GF9102ACPM |
2
521 - 26 - 02
CLK
42
I
System Clock.
TTL input. All timing specifications are referenced to the rising edge of clock.
SYNC
43
I
Data Synchronization.
TTL input with internal pull-up. This input is used to synchronize the
incoming data with the GF9102A by holding SYNC high on clock N and low on clock N+1 when
the first data word is presented to the input SI
11..0
. SYNC may be held low until
resynchronization is desired, or it may be clocked at half the clock rate.
SI
11..0
40, 37, 36, 35,
34, 33, 32, 31,
30, 27, 26, 25
I
Input Data Port.
TTL inputs with internal pull-downs. Data is presented to this registered 12-bit
data input port. This port can be programmed as two’s complement signed or unsigned binary
format. See the following section on input data format. Data is latched internally on every clock in
decimate mode, and on every other clock in interpolate mode. SI
11
is the MSB.
Two’s Complement Output Format Control.
TTL input with internal pull-down. When TCO is high,
output data is presented in two’s complement format. When TCO is low, the output is inverted
offset binary, obtained by inverting bits SO
14
through SO
0
, leaving SO
15
unchanged.
Interpolate.
Active low TTL input with internal pull-up. When the interpolate control is low, data
is input at full clock speed and the chip inserts zeros between samples, padding the input to
match the output rate. The GF9102A then interpolates between these alternate input data points to
achieve full output data rate.
DEC
1
I
Decimate.
Active low TTL input with internal pull-down. When the decimate control is low, the
output register is driven at half system clock speed, decimating the output data stream. When
DEC and INT are low, the GF9102A will be programmed as a 21 tap or 9 tap bandpass filter
depending on the state of the SYNC input. See Operation Mode Control below for more detail.
Output Rounding Control.
TTL inputs with internal pull-down. These pins set the position of the
effective least significant bit of the output port by adding a rounding bit to the next lower internal bit
and zeroing all outputs below the rounding bit. Additional rounding functions are added with the
SO
1
control input. See Table 6.
Output Data Port.
TTL outputs (SO
3..0
are bi-directional pins with an internal pull-down). The
filtered result is available at this registered 16-bit output port, half LSB rounded as determined by
the rounding control word RND
2..0
. SO
15
is the MSB. The SO
3..0
control inputs enable additional
formatting and rounding features as described below.
Output Data Port.
TTL bi-directional pins with internal pull-down. The SO
0
control input enables
the unsigned input and output format. The SO
1
control input enables 8-bit rounding or CCIR 601
8-bit and 10-bit modes of operation. SO
3..2
are reserved for future functions.
Output Enable.
Active low TTL input with internal pull-up. When this asynchronous input is high,
the output data port is in the high impedance state.
+5 V
±
5% power supply.
Ground
PIN DESCRIPTION
SYMBOL
PIN NO.
TYPE
DESCRIPTION
TCO
2
I
INT
44
I
RND
2..0
22, 23, 24
I
SO
15..0
4, 5, 6, 7,
8, 9, 10, 11,
14, 15, 16, 17,
18, 19, 20, 21
O
SO
3..0
18, 19, 20, 21
I/O
OE
3
I
VDD
13, 29, 38
GND
12, 28, 39, 41
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| GF9102ACTM | 制造商:Gennum Corporation 功能描述: |
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