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| 型號： | GA81032T-5T |
| 英文描述： | x32 Fast Synchronous SRAM |
| 中文描述： | X32號，快速同步SRAM |
| 文件頁數(shù)： | 8/23頁 |
| 文件大小： | 756K |
| 代理商： | GA81032T-5T |
Rev: 1.00 12/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
8/23
2000, Giga Semiconductor, Inc.
GS81032T/Q-150/138/133/117/100/66
Simplified State Diagram with G
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1.
2.
The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (read cycles with G high) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.
Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off, and for incoming data to meet
Data Input Set Up Time.
3.
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