參數(shù)資料
型號(hào)： GA81032T-5T
英文描述： x32 Fast Synchronous SRAM
中文描述： X32號(hào)，快速同步SRAM
文件頁(yè)數(shù)： 5/23頁(yè)
文件大?。?/td> 756K
代理商： GA81032T-5T
Rev: 1.00 12/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
5/23
2000, Giga Semiconductor, Inc.
GS81032T/Q-150/138/133/117/100/66
Mode Pin Functions
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Byte Write Truth Table
Notes:
1.
2.
3.
All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
Byte Write Enable inputs B
A
, B
B
, B
C
and/or B
D
may be used in any combination with BW to write single or multiple bytes.
All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Mode Name
Pin Name
State
L
H or NC
L
H or NC
L or NC
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
H
Function
GW
BW
B
A
B
B
B
C
B
D
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte
A
H
L
L
H
H
H
2, 3
Write byte
B
H
L
H
L
H
H
2, 3
Write byte
C
H
L
H
H
L
H
2, 3, 4
Write byte
D
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0]
00
01
10
11
A[1:0]
01
10
11
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
1st address
2nd address
3rd address
4th address
A[1:0]
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
1st address
2nd address
3rd address
4th address
相關(guān)PDF資料
PDF描述
GA81032T-6 x32 Fast Synchronous SRAM
GA81032T-6I x32 Fast Synchronous SRAM
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