Ver: 2.4
May 23, 2003
TEL: 886-3-5788833
http://www.gmt.com.tw
12
G767
Global Mixed-mode Technology Inc.
Valid A/D conversion results for both channels are
available one total conversion time (125ms nominal,
156ms maximum) after initiating a conversion, whether
conversion is initiated via the RUN/STOP bit, hard-
wareSTBY pin, one-shot command, or initial power-up.
Changing the conversion rate can also affect the delay
until new results are available. See Table 8.
Slave Addresses
The G767 appears to the SMBus as one device hav-
ing a common address for both ADC channels. The
device address can be set to one of nine different val-
ues by pin-strapping ADD0 and ADD1 so that more
than one G767 can reside on the same bus without
address conflicts (Table 9).
The address pin states are checked at POR only, and
the address data stays latched to reduce quiescent
supply current due to the bias current needed for
high-Z state detection.
The G767 also responds to the SMBus Alert Re-
sponse slave address (see the Alert Response Ad-
dress section).
POR AND UVLO
The G767 has a volatile memory. To prevent ambiguous
power-supply conditions from corrupting the data in
memory and causing erratic behavior, a POR voltage
detector monitors Vcc and clears the memory if Vcc falls
below 1.7V (typical, see Electrical Characteristics table).
When power is first applied and Vcc rises above 1.75V
(typical), the logic blocks begin operating, although reads
and writes at V
CC
levels below 3V are not recommended.
A second Vcc comparator, the ADC UVLO comparator,
prevents the ADC from converting until there is sufficient
headroom (Vcc = 2.8V typical).
Table 9.Slave Address Decoding (ADD0 and ADD1)
ADD0
GND
GND
GND
High-Z
High-Z
High-Z
Vcc
Vcc
Vcc
ADD1
GND
High-Z
Vcc
GND
High-Z
Vcc
GND
High-Z
Vcc
ADDRESS
0011 000
0011 001
0011 010
0101 001
0101 010
0101 011
1001 100
1001 101
1001 110
Note: High-Z means that the pin is left unconnected
and floating.
Power-Up Defaults:
Interrupt latch is cleared.
Address select pins are sampled.
ADC begins auto-converting at a 0.25Hz rate.
Command byte is set to 00h to facilitate quick re-
mote Receive Byte queries.
T
HIGH
and T
LOW
registers are set to max and min
limits, respectively.