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參數(shù)資料
| 型號(hào)： | G1432F3U |
| 廠(chǎng)商： | Global Mixed-mode Technology Inc. |
| 元件分類(lèi)： | 音頻放大器 |
| 英文描述： | 2W Stereo Audio Amplifier |
| 中文描述： | 2W立體聲音頻放大器 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 340K |
| 代理商： | G1432F3U |
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Ver: 1.1
Jun 21, 2006
TEL: 886-3-5788833
http://www.gmt.com.tw
13
G1432
Global Mixed-mode Technology Inc.
Optimizing DEPOP Operation
Circuitry has been implemented in the G1432 to
minimize the amount of popping heard at power-up
and when coming out of shutdown mode. Popping
occurs whenever a voltage step is applied to the
speaker and making the differential voltage gener-
ated at the two ends of the speaker. To avoid the
popping heard, the bypass capacitor should be
chosen promptly, 1/(CBx100kΩ) ≦ 1/(CI*(RI+RF)).
Where 100k
Ω is the output impedance of the
mid-rail generator, CB is the mid-rail bypass ca-
pacitor, CI is the input coupling capacitor, RI is the
input impedance, RF is the gain setting impedance
which is on the feedback path. CB is the most im-
portant capacitor. Besides it is used to reduce the
popping, CB can also determine the rate at which
the amplifier starts up during startup or recovery
from shutdown mode.
De-popping circuitry of the G1432 is shown on Fig-
ure B. The PNP transistor limits the voltage drop
across the 50k
Ω by slewing the internal node slowly
when power is applied. At start-up, the voltage at
BYPASS capacitor is 0. The PNP is ON to pull the
mid-point of the bias circuit down. So the capacitor
sees a lower effective voltage, and thus the charg-
ing is slower. This appears as a linear ramp (while
the PNP transistor is conducting), followed by the
expected exponential ramp of an R-C circuit.
Bypass
VDD
100 k
Ω
100 k
Ω
50 k
Ω
Figure B
Bypass
VDD
100 k
Ω
100 k
Ω
50 k
Ω
Figure B
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相關(guān)代理商/技術(shù)參數(shù) |
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