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參數(shù)資料
| 型號： | FZE1658G |
| 廠商： | SIEMENS A G |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 8 x Digital Sensor Interface |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 406K |
| 代理商： | FZE1658G |
FZE 1658G
Semiconductor Group
8
1)
Input voltages may rise before the supply voltage.
Full function at
V
S
>
V
VSRO
(see Characteristics).
2)
Limits GND potential difference at minimum supply voltage.
3)
Also applies to several cascaded FZE 1658G (note dependence with clock frequency).
For definition of timing items, see timing diagram.
Operating Range
Parameter
Symbol
Limit Values
Unit
Notes
min.
max.
Supply voltage
V
S
10
48
V
Note power
dissipation
1)
Supply voltage rise
SR
VS
– 0.1
1
V/
μ
s
Supply voltage
V
S
-
V
DGND
9
V
2)
GND potential difference
V
DGND
– 1.5
1.5
V
Input terminal current
I
IT
– 10
10
mA
Input voltage SE-N, T, LO-N
V
IH
V
IL
2.8
– 0.5
6
1.7
V
V
Input current SE-N, T, LO-N
I
I
– 1
1
mA
Clamp current
Junction temperature
T
j
– 25
150
°
C
Ambient temperature
T
A
– 25
105
°
C
Dependent on
R
th
Clock frequency
f
T
1
MHz
Clock pulse width H or L
t
TH
,
t
TL
300
ns
SE-N set up time to T
↑
t
VSE
300
ns
LO-N set up time to T
↑
t
VLO
1.2
μ
s
SE-N, LO-N, T rise and fall time
within thresholds
t
r
,
t
f
3
μ
s
3)
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