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參數(shù)資料
| 型號(hào)： | FTF3020-C |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full Frame CCD Image Sensor |
| 中文描述： | 全幀CCD圖像傳感器 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 212K |
| 代理商： | FTF3020-C |
1999 November
5
Philips Semiconductors
Product specification
Full Frame CCD Image Sensor
FTF3020-C
1
During Charge Reset it is allowed to exceed maximum rating levels (see note
5
).
2
All voltages in relation to SFS.
3
To set the VNS voltage for optimal Vertical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values.
4
Three-level clock is preferred for maximum charge; the swing during vertical transport should be 4V higher than the voltage during integration.
A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed.
5
Charge Reset can be achieved in two ways:
The typical A-clock low level is applied to all image clocks; for proper CR, an additional Charge Reset pulse on VNS is required (preferred).
The typical CR level is applied to all image clocks simultaneously.
Specifications
DC CONDITIONS
2
MIN. [V]
TYPICAL [V]
MAX. [V]
MAX. [mA]
VNS
VPS
SFD
SFS
VCS
OG
RD
3
N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
Output Gate
Reset Drain
18
1
16
0
-5
4
13
24
3
20
0
0
6.5
15.5
28
7
24
0
3
8
18
15
15
4.5
1
-
-
-
AC CLOCK LEVEL CONDITIONS
2
MIN.
TYPICAL
MAX.
UNIT
IMAGE CLOCKS:
A-clock amplitude during integration and hold
A-clock amplitude during vertical transport (duty cycle=5/8)
A-clock low level
Charge Reset (CR) level on A-clock
4
5
8
10
-5
10
14
0
-5
V
V
V
V
OUTPUT REGISTER CLOCKS:
C-clock amplitude (duty cycle during hor. transport = 3/6)
C-clock low level
Summing Gate (SG) amplitude
Summing Gate (SG) low level
4.75
2
5
3.5
10
3.5
5.25
10
V
V
V
V
OTHER CLOCKS:
Reset Gate (RG) amplitude
Reset Gate (RG) low level
Charge Reset (CR) pulse on Nsub
5
5
0
10
3
10
10
10
V
V
V
ABSOLUTE MAXIMUM RATINGS
1
MIN.
MAX.
UNIT
GENERAL:
storage temperature
ambient temperature during operation
voltage between any two gates
DC current through any clock phase (absolute value)
OUT current (no short circuit protection)
-55
-40
-20
-0.2
0
+80
+60
+20
+2.0
10
°C
°C
V
μA
mA
VOLTAGES IN RELATION TO VPS:
VNS, SFD, RD
VCS, SFS
all other pins
-0.5
-8
-5
+30
+5
+25
V
V
V
VOLTAGES IN RELATION TO VNS:
SFD, RD
VCS, SFS, VPS
all other pins
-15
-30
-30
+0.5
+0.5
+0.5
V
V
V
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