參數(shù)資料
型號(hào)： FT2232HL-TRAY
廠商： Future Technology Devices International Ltd
元件分類： 總線控制器
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： LEAD FREE, LQFP-64
文件頁(yè)數(shù)： 36/63頁(yè)
文件大?。?/td> 1598K
代理商： FT2232HL-TRAY
Copyright 2010 Future Technology Devices International Limited
41
Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 2.10
Clearance No.: FTDI#77
WRSTB#
RDSTB#
Figure 4.19 Synchronous Bit-Bang Mode Timing Interface Example
Name
Description
t1
Current pin state is read
t2
RDSTB# is set inactive and data on the paralle I/O pins is read and sent to the USB host.
t3
RDSTB# is set active again, and any pins that are output will change to their new data
t4
1 clock cycle to allow for data setup
t5
WRSTB# goes active. This indicates that the host PC has written new data to the I/O parallel data pins
t6
WRSTB# goes inactive
Table 4.10 Synchronous Bit-Bang Mode Timing Interface Example Timings
WRSTB# = this output indicates when new data has been written to the I/O pins from the Host PC (via
the USB interface).
RDSTB# = this output rising edge indicates when data has been read from the I/O pins and sent to the
Host PC (via the USB interface).
The WRSTB# goes active in t4. The WRSTB# goes active when data is read from the USB RXFIFO (i.e.
sent from the PC). The RDSTB# goes inactive when data is sampled from the pins and written to the USB
TXFIFO (i.e. sent to the PC). The SETUP command to the FT2232H is used to setup the bit-mode. This
command also contains a byte wide data mask to set the direction of each bit. The direction on each pin
doesnt change unless a new SETUP command is used to modify the direction.
The WRSTB# and RDSTB# strobes are only a guide to what may be happening depending on the
direction of the bus. For example if all pins are configured as inputs, it is still necessary to write to these
pins in order to get the FT2232H to read those pins even though the data written will never appear on
the pins.
Signals and data-flow are illustrated in Figure 4.20
USB Rx
FIFO/
Buffer
Parallel I/O
data
Parallel
I/O pins
USB
WRSTB#
RDSTB#
USB Tx
FIFO/
Buffer
Figure 4.20 Bit-bang Mode Dataflow Illustration Diagram.
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