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參數(shù)資料
| 型號： | FSTU162450MTD |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Configurable 4-Bit to 20-Bit Bus Switch with .2V Undershoot Protection and 25з Series Resistors in Outputs (Preliminary) |
| 中文描述： | CBT/FST/QS/5C/B SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 476K |
| 代理商： | FSTU162450MTD |
Preliminary
7
www.fairchildsemi.com
F
AC Electrical Characteristics
Note 9:
This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
(Note 10)
Note 10:
T
A
=
+
25
°
C, f
=
1 MHz, Capacitance is characterized but not tested.
Symbol
Parameter
T
A
=
40
°
C to
+
85
°
C,
C
L
=
50pF, RU
=
RD
=
500
V
CC
=
4.5 – 5.5V
Min
Max
0.25
Units
Conditions
Figure
V
CC
=
4.0V
Min
Number
Max
0.25
t
PHL
, t
PLH
Propagation Delay Bus-to-Bus
(Note 9)
Output Enable Time
ns
V
I
=
OPEN
Figures
2, 3
Figures
2, 3
t
PZH
, t
PZL
1.5
5.5
6.0
ns
V
I
=
7V for t
PZL
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PLZ
V
I
=
OPEN for t
PHZ
V
I
=
7V for t
PZL
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PLZ
V
I
=
OPEN for t
PHZ
t
PHZ
, t
PLZ
Output Disable Time
1.5
5.5
6.0
ns
Figures
2, 3
t
PZH
, t
PZL
Sel (S
0, 1
) to Output Enable Time
1.5
6.0
6.5
ns
Figures
2, 3
t
PHZ
, t
PLZ
Sel (S
0, 1
) to Output Disable Time
1.5
6.0
6.5
ns
Figures
2, 3
Symbol
Parameter
Typ
Max
Units
Conditions
C
IN
Control Pin Input Capacitance
3
pF
V
CC
=
5.0V, V
IN
=
0V
C
I/O
Input/Output Capacitance
“
OFF State
”
6
pF
V
CC
, OE
=
5.0V, V
IN
=
0V
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