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參數(shù)資料
| 型號(hào)： | FSSD07UMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MUX 2:1 SD/SDIO/MMC 24-UMLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 多路復(fù)用器 |
| 應(yīng)用： | 手機(jī)，數(shù)碼相機(jī)，媒體播放器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-UFQFN |
| 供應(yīng)商設(shè)備封裝： | 24-UMLP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1219 (CN2011-ZH PDF) |
| 其它名稱： | FSSD07UMXDKR |
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2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSSD07 Rev. 1.0.2
4
FSSD07
—
1-Bit
/
4-Bit
SD/SDIO
and
MMC
Dual-Host
Multiplexer
Functional Description
The FSSD07 enables the multiplexing of dual ASIC /
baseband processor hosts to a common peripheral card
or module, providing bi-directional support of the dual-
voltage SD/SDIO or MMC cards available in the
marketplace. Each host SDIO port has its own supply
rail, such that hosts with different supplies can be
interfaced to a common peripheral module or card. The
peripheral card supply must be equal to or greater than
the host(s) to minimize power consumption. The
independent VDDC, VDDH1, and VDDH2 are defined by the
supplies
connected
from
the
application
Power
Management ICs (PMICs) to the FSSD07. The clock
path is a uni-directional buffered path rather than a bi-
directional switch port. The supplies (VDDC, VDDH1, and
VDDH2) have an internal termination resistor (typically
3M
) to ensure the supply rails internally do not float if
the application turns off one or all of these sources.
CMD, DAT Bus Pull-ups
The CMD and DAT[3:0] ports do not have, internally, the
system pull-up resistors as defined in the MMC or SD
card system bus specifications. The system bus pull-up
must be added external to the FSSD07. The value,
within the specific specification limits, is a function of the
individual application and type of card or peripheral
connected. For SD card applications, the RCMD and RDAT
pull-ups should be between 10k and 100k. For MMC
applications, the RCMD pull-ups should be between
4.7k and 100k, and the RDAT pull-ups between 50k
and 100k. The card-side CMD and DAT[3:0] outputs
have a circuit that facilitates incident wave switching, so
the external pull-up resistors ensure retention of the
output high level.
The OE pin can be used to place the CMD and DAT[3:0]
into high-impedance mode during power-up sequencing
or when the system enters IDLE state (see IDLE State
CMD/DAT Bus “Parking”
).
CLK Bus
The 1CLK and 2CLK inputs are bi-state buffer
architectures, rather than a switch I/O, to ensure 52MHz
incident wave switching. Since most host controllers
also have a clock enable register bit to enable or disable
the system clock when in IDLE mode, the CLK output is
not disabled by the OE pin. Instead, the CLK output is a
function of whichever host controller clock is selected by
the S pin.
Consequently, there is always a clock path connected
between the selected host and the card. The state of the
CLK pin is a function of the selected host controller
nCLK output pin, which facilitates retaining clock duty
cycle in the system or performing read / wait operations.
IDLE State & Power-Up CMD/DAT Bus
“Parking”
The SD and MMC card specifications were written for a
direct point-to-point communication between host
controller and card. The introduction of the FSSD07 in
that path, as an expander, requires that the functional
operation and system latency not be impacted by the
switch characteristics. Since there are various card
formats, protocols, and configurable controllers, an OE
pin is available to facilitate a fast IDLE transition for the
CMD/DAT[3:0] outputs. Some controllers, rather than
placing CMD/DAT into high-impedance mode, pull the
outputs HIGH for a clock cycle prior to going into high-
impedance mode (referred to as “parking” the output).
Some legacy controllers pull their outputs HIGH versus
high impedance.
If the OE pin is pulled HIGH and the controller places its
command and data outputs into high-impedance (driving
nCMD/nDAT[3:0]), the FSSD07 CMD/DAT[3:0] output
rise time is a function of the RC time constant through
the switch path. Pulling OE LOW puts the switches into
high impedance, disabling communication from the host
to card, and the CMD/DAT[3:0] outputs are pulled HIGH
by the system pull-up resistors chosen for the
application.
This
mechanism
facilitates
power-up
sequencing by holding OE LOW until supplies are stable
and communication between the host(s) and card is
enabled.
Power Optimization
Since the FSSD07 has multiple supplies (VDDC, VDDH1,
and VDDH2), the control signals have been referenced to
the card peripheral side (VDDC). To minimize power
consumption, current paths between supplies are
isolated when one or more supplies are not present.
This includes the configuration of the removal of VDDC
with host controller supplies remaining present.
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