參數(shù)資料
型號(hào)： FSA9288AUMX
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 27/30頁(yè)
文件大?。?/td> 0K
描述： IC USB MULTIMEDIA SWITCH 20-UMLP
標(biāo)準(zhǔn)包裝： 5,000
功能： USB 開(kāi)關(guān)
電路： 3:1
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3 V ~ 4.4 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-UFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 20-UMLP（4x3）
包裝： 帶卷 (TR)
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A Rev 1.1.0
6
FS
A9
2
80A
—
US
B
Po
rt
Mu
lt
im
edia
Swi
tc
h
,
Fea
turi
n
g
Automatic
Se
lect
a
nd
Ac
ces
s
ory
Detection
2. Power-up & Reset
The FSA9280A does not need special power sequencing for
correct operation. The main power of the device is provided
by either VBUS_IN or VBAT. If VBUS_IN is not present and VBAT is
applied, VBAT is used to power the device. VDDIO is only used
for I
2C interface and interrupt processing.
Table 1 summarizes the enabled features of each power
state of the FSA9280A. The valid voltages levels for each
power supply can be found in Section 9.2.
Table 1
– Power States Summary
Notes:
1.
VDDIO is expected to be the same supply used by the baseband I/Os.
2.
This is not a typical state: both VBAT and VDDIO are typically provided simultaneously.
2.1. Reset
When the device is reset, all the registers are initialized to
the default values shown in Table 7 and all switch paths are
open. After reset or power up, the FSA9280A enters
Standby Mode and is ready to detect accessories sensed on
its VBUS_IN and / or ID_CON pins.
2.1.1.
Hardware Reset
There are three hardware reset mechanisms:
Power-on reset caused by the initial rising edge of V
BUS
or VBAT
The falling edge of V
DDIO.
With V
DDIO valid, driving both I2C_SDA and I2C_SCL
signals LOW for at least 30ms.
Note:
3.
I
2C controllers that implement clock stretching could
cause reset. In this case, GPIOs could be used for the
I
2C interface.
2.1.2.
Software Reset
The device can be reset through software by writing to the
Reset bit in the Register (1BH).
Valid
VBUS_IN
Valid
VBAT
Valid
VDDIO
(1)
Power
State
Enabled Functionality
Charging
through FET
Processor Communication
(I
2C & Interrupts)
Detection
NO
Power Down
NO
YES
(2)
ILLEGAL STATE
NO
YES
NO
Powered from VBAT
NO
YES
NO
YES
Powered from VBAT
NO
YES
NO
Powered from VBUS_IN
Yes
NO
YES
NO
Powered from VBAT
YES
NO
YES
NO
YES
(2)
Powered from VBUS_IN
YES
Powered from VBAT
YES
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