參數(shù)資料
型號： FSA9288AUMX
廠商： Fairchild Semiconductor
文件頁數(shù)： 11/30頁
文件大?。?/td> 0K
描述： IC USB MULTIMEDIA SWITCH 20-UMLP
標準包裝： 5,000
功能： USB 開關
電路： 3:1
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3 V ~ 4.4 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-UFQFN 裸露焊盤
供應商設備封裝： 20-UMLP（4x3）
包裝： 帶卷 (TR)
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A Rev 1.1.0
19
FS
A9
2
80A
—
US
B
Po
rt
Mu
lt
im
edia
Swi
tc
h
,
Fea
turi
n
g
Automatic
Se
lect
a
nd
Ac
ces
s
ory
Detection
9.6. I
2C Controller DC Characteristics
Symbol
Parameter
Fast Mode (400kHz)
Min.
Max.
Units
VIL
Low-Level Input Voltage
-0.5
0.3VDDIO
V
VIH
High-Level Input Voltage
0.7VDDIO
V
VHYS
Hysteresis of Schmitt Trigger Inputs
VDDIO>2V
0.05VDDIO
V
VDDIO<2V
0.1VDDIO
VOL1
Low-Level Output Voltage at 3mA Sink Current
(Open-Drain)
VDDIO>2V
0
0.4
V
VDDIO<2V
0.2VDDIO
II2C
Input Current of I2C_SDA and I2C_SCL Pins, Input Voltage 0.26V to 2.34V
-10
10
A
CI
Capacitance for Each I/O Pin
10
pF
9.7. I
2C AC Electrical Characteristics & Register Map
Symbol
Parameter
Fast Mode
Min.
Max.
Unit
fSCL
SCL Clock Frequency
0
400
kHz
tHD;STA
Hold Time (Repeated) START Condition
0.6
s
tLOW
LOW Period of SCL Clock
1.3
s
tHIGH
HIGH Period of SCL Clock
0.6
s
tSU;STA
Set-up Time for Repeated START Condition
0.6
s
tHD;DAT
Data Hold Time
0
0.9
s
tSU;DAT
Data Set-up Time
100
ns
tr
Rise Time of SDA and SCL Signals
20+0.1Cb
300
ns
tf
Fall Time of SDA and SCL Signals
20+0.1Cb
300
ns
tSU;STO
Set-up Time for STOP Condition
0.6
s
tBUF
BUS-Free Time between STOP and START Conditions
1.3
s
tSP
Pulse Width of Spikes that Must Be Suppressed by the Input Filter
0
50
ns
Notes:
22. A fast-mode I
2C-Bus device can be used in a standard-mode I2C-Bus system, but the requirement t
SU;DAT ≥
be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device
does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr_max + tSU;DAT = 1000 + 250
= 1250ns (according to the standard-mode I
2C bus specification) before the SCL line is released.
23. Cb equals the total capacitance of one BUS line in pF. If mixed with high-speed devices, faster fall times are allowed
according to the I
2C specification.
Figure 23.
Definition of Timing for Full-Speed Mode Devices on the I
2C Bus
Table 6. I
2C Slave Address
Name
Size (Bits)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Slave Address
8
0
1
0
1
0
1
R/W
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