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參數(shù)資料
| 型號： | FS8160 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.1 GHz/1.1 GHz Dual Phase-locked Loop IC |
| 中文描述： | 1.1 GHz/1.1 GHz雙鎖相環(huán)集成電路 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 257K |
| 代理商： | FS8160 |
FS8160
Page 7
April 2003
Phase/Frequency Detector (PFD)
The PFD compares an internal input frequency divider output signal,
f
V
, with an internal
reference frequency divider output signal,
f
R
, and generates an error signal which is pro-
portional to the phase error between
f
V
and
f
R
. The polarity of the PFD is user-selectable
using serial input data control bits (see Table 5 on page 9). The input/output waveforms
for a positive polarity PFD (VCO frequency increases with increasing tuning voltage) are
shown in Fig. 1.
Fig. 1 – Positive polarity PFD input/output waveforms
Charge Pump
The charge pump output sources/sinks current to/from an external loop filter, which con-
verts the charge into a voltage used to control the external VCO’s frequency. When the
PLL is locked, the charge pump output is primarily in a high impedance (high-Z) state.
The magnitude of the charge pump output current is user-selectable using serial input data
control bits (see Table 5 on page 9).
Serial Input Data Format
The divide ratios for the input (
N
) and reference (
R
) dividers are input using an 18-bit
serial interface consisting of separate clock (CLK), data (DATA), and latch enable (LE)
lines. The format of the serial data is shown in Fig. 2.
Fig. 2 – Serial input data format
The data on the DATA line is written to the shift register on the rising edge of the CLK
signal and is input with MSB first. The data on the DATA line should be changed on the
falling edge of CLK, and LE should be held low while data is being written to the shift
register. Data is transferred from the shift register to one of the four (4) frequency divider
latches when LE is set high depending upon the state of the control bits (CB[1:0]) as indi-
high-Z
high-Z
high-Z
f
R
f
V
DOM, DOA
DATA[15:0]
CB[1:0]
M
L
17
0
1
2
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