參數(shù)資料
型號(hào)： FS6011-02
廠商： Electronic Theatre Controls, Inc.
英文描述： DIGITAL AUDIO/VIDEO CLOCK GENERATOR IC
中文描述： 數(shù)字音頻/視頻時(shí)鐘發(fā)生器IC
文件頁(yè)數(shù)： 4/15頁(yè)
文件大?。?/td> 234K
代理商： FS6011-02
XT
July 1998
4
7.20.98
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4.1
The ACLK frequency is controlled by register bits D[0],
D[1], and D[2] accessed via the serial interface. The
ACLK frequencies listed below are derived via the PLL
Divider Ratio from a reference frequency of 27MHz.
Audio PLL Clock Frequencies (ACLK)
Table 3: ACLK Frequency Select
D[2]
D[1]
D[0]
PLL DIVIDER
RATIO
AUDIO
OVERSAMPLING
ACLK
(MHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1024 / 2250
1024 / 3375
1024 / 4500
1024 / 6750
1568 / 3750
1568 / 2500
1568 / 7500
1024 / 1125
48kHz x 256
32kHz x 256
48kHz x 256 / 2
32kHz x 256 / 2
44.1kHz x 256
44.1kHz x 384
44.1kHz x 256 / 2
48kHz x 512
12.288
8.192
6.144
4.096
11.2896
16.9344
5.6448
24.576
NOTE: Contact AMI for custom PLL frequencies
4.2
The ACLK frequencies shown may be smoothly modified
to a slightly higher or lower value under register control.
Register bit D[3] must be a logic-one to activate this
mode. The value of D[4] controls whether the frequency
will be adjusted slightly low (D[4] = 0) or high (D[4] = 1).
Audio Clock Off-Speed Frequencies
Table 4: Audio Off Speed Frequencies
D[4]
D[3]
D[2]
D[1]
D[0]
PLL DIVIDER
RATIO
ACLK
(MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1023 / 2250
1023 / 3375
1023 / 4500
1023 / 6750
1567 / 3750
1567 / 2500
1567 / 7500
1023 / 1125
1025 / 2250
1025 / 3375
1025 / 4500
1025 / 6750
1569 / 3750
1569 / 2500
1569 / 7500
1025 / 1125
12.276
8.184
6.138
4.092
11.2824
16.9236
5.6412
24.5520
12.3000
8.2000
6.1500
4.1000
11.2968
16.9432
5.6484
24.6000
4.3
The UCLK frequency is controlled by register bits D[5],
D[6] and D[7], accessed via the serial interface. UCLK
frequencies listed below are derived via the PLL Divider
Ratio from a reference frequency of 27MHz.
Utility PLL Clock Frequencies (UCLK)
Table 5: UCLK Frequency Select
D[7]
D[6]
D[5]
PLL DIVIDER RATIO
UCLK (MHz)
0
0
0
16 / 27
16.0000
0
0
1
35 / 33
28.6363
0
1
0
1568 / 3750
11.2896
0
1
1
1
27.0000
1
0
0
544 / 375
39.1680
1
0
1
728 / 375
52.4160
1
1
0
10 / 9
30.0000
1
1
1
1024 / 1125
24.5760
NOTE: Contact AMI for custom PLL frequencies
4.4
The PCLK frequency is controlled by the logic levels on
the PSEL0 and PSEL1 inputs. These inputs have weak
pull-downs. PCLK frequencies listed below are derived
via the PLL Divider Ratio from a reference frequency of
27MHz.
Processor PLL Frequencies (PCLK)
Table 6: PCLK Frequency Select
PSEL1
PSEL0
PLL DIVIDER RATIO
PCLK (MHz)
0
0
32 / 27
32.0000
0
1
40 / 27
40.0000
1
0
50 / 27
50.0000
1
1
60 / 41
39.5122
NOTE: Contact AMI for custom PLL frequencies
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