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參數(shù)資料
| 型號(hào)： | FR65E |
| 廠商： | Fujitsu Limited |
| 英文描述： | 32-Bit Microcontroller |
| 中文描述： | 32位微控制器 |
| 文件頁(yè)數(shù)： | 60/87頁(yè) |
| 文件大?。?/td> | 369K |
| 代理商： | FR65E |
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MB91307B
60
9.
DMAC (DMA Controller)
(1) Overview
This module is used to accomplish DMA (Direct Memory Access) transfer on FR family devices.
DMA transfer controlled by this module increases system performance by enabling high speed transfer of many
types of data without going through the CPU.
Hardware Configuration
This module is principally configured from the following units:
Five independent DMA channels
5-channel independent access control circuit
32-bit address registers (reload enabled: 2 per channel)
16-bit transfer count registers (reload enabled: 2 per channel)
4-bit block count registers (1 per channel)
External transfer request input pins: DREQ0,DREQ1,DREQ2 (ch0,1,2 only)
External transfer request acknowledge output pins: DACK0,DACK1,DACK2 (ch0,1,2 only)
DMA output completed pins: DEOP0,DEOP1,DEOP2 (ch0,1,2 only)
Fly-by transfer (memory to I/O, memory to memory) (ch0,1,2 only)
Two-cycle transfer
Principal Functions
Data transfer using the DMAC module primarily involves the following functions:
Supports independent data transfer on multiple channels (5 ch)
(1) Order of priority (ch.0
>
ch.1
>
ch.2
>
ch.3
>
ch.4)
(2) The order can be reversed between ch.0-ch.1.
(3) DMAC startup sources
Input from an external-only pin (edge detection/level detection, ch0,1,2 only)
Request from a built-in peripheral (shared interrupt request, including external interrupts)
Software request (register write)
(4) Transfer modes
Demand transfer / burst transfer / step transfer / block transfer
Addressing mode 32-bit full address designation (increment/decrement/fixed)
(address increment can be specified up to -255 to +255)
Data type, byte / half-word / word length
Single-shot / reload selection available
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