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參數(shù)資料
| 型號： | FQU6N50C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | JFETs |
| 英文描述： | These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary planar stripe, DMOS technology |
| 中文描述： | 4.5 A, 500 V, 1.2 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | IPAK-3 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 687K |
| 代理商： | FQU6N50C |
Rev. B, June 2004
F
2004 Fairchild Semiconductor Corporation
Typical Characteristics
(Continued)
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs Case Temperature
Figure 11. Transient Thermal Response Curve
t
1
P
DM
t
2
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 8. On-Resistance Variation
vs Temperature
-100
-50
0
50
100
150
200
0.8
0.9
1.0
1.1
1.2
Notes :
※
1. V
= 0 V
2. I
D
= 250 μA
B
D
,
D
T
J
, Junction Temperature [
o
C]
-100
-50
0
50
100
150
200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Notes :
※
1. V
GS
= 10 V
2. I
D
= 2.25 A
R
D
,
D
T
J
, Junction Temperature [
o
C]
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-2
10
-1
10
0
Notes :
1. Z
(t) = 2.05
2. Duty Factor, D=t
1
/t
2
3. T
JM
- T
C
= P
DM
* Z
θ
JC
(t)
※
/W Max.
℃
single pulse
D=0.5
0.02
0.2
0.05
0.1
0.01
Z
θ
(
t
1
, Square W ave Pulse Duration [sec]
25
50
75
100
125
150
0
1
2
3
4
5
I
D
,
T
C
, Case Temperature [ ]
℃
10
0
10
1
10
2
10
3
10
-2
10
-1
10
0
10
1
10
2
100 ms
1 ms
DC
10 ms
100
μ
s
Operation in This Area
is Limited by R
DS(on)
Notes :
※
1. T
C
= 25
2. T
= 150
3. Single Pulse
o
C
o
C
I
D
,
V
DS
, Drain-Source Voltage [V]
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