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參數(shù)資料
| 型號： | FPD87392BXB |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) |
| 中文描述： | 3.3 TFT - LCD的雙LVDS輸入定時(shí)控制器/雙⑩輸出區(qū)特別職務(wù)隊(duì)的TFT - LCD顯示器和筆記本電腦（SXGA / SXGA / UXGA）下 |
| 文件頁數(shù)： | 27/30頁 |
| 文件大?。?/td> | 1980K |
| 代理商： | FPD87392BXB |
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Pin Description
Control Input
(Continued)
Symbol
Pin No.
37, 38
122, 33
Type
I
I
Function
BIT_CFG1/2
MODE[1:0]
LVDS Input and RSDS Output Bit Selection
Graphic Mode Selection
“00”: SXGA, “01”: SXGA+, “10”: UXGA, “11”: Don’t Care
RSDS Output Data Mapping
TP Duty Control (Default Low)
OE Duty Control (Default 2’b00)
Test Mode
Low: Normal Operation, High: Test Mode
LVDS Power Down (Active Low)
System Reset (Active Low)
RxMap=1(SS Mapping); RxMap=0, NS Mapping
No Connect
DMAP1/2
TPW
OEW1/2
TEST1/2
39, 40
125
126, 127
128, 1
I
I
I
I
PDI
RSTB
RxMap
NC
32
34
120
I
I
I
111, 116
Power Supply
Symbol
Pin No.
36, 42, 109,
117, 123
35, 41, 112,
118, 124
2, 16, 17,
31
3, 14, 15,
18, 29, 30
55, 75, 86,
106
46, 64, 77,
97
Type
P
Function
V
DD
Digital Power for Logic Core and LVDS Deserializer
V
SS
G
Digital Ground for Logic Core and LVDS Deserializer
V
DDA
P
Power for LVDS PLL and Analog Bandgap
V
SSA
G
Ground for LVDS PLL and Analog Bandgap
V
DDIO
P
Digital I/O Power and RSDS Outputs
V
SSIO
G
Digital I/O Ground and RSDS Outputs
Bonding Option (B/O)
Symbol
Pin No.
B/O
Type
PU
Function
SYNC
SYNC Mode
High: Enable, Low: Disable
Free Run Mode
High: Enable, Low: Disable
Failure Detection
High: Enable, Low: Disable
Power-On-Reset
High: Enable, Low: Disable
FRM
B/O
PU
FDE
B/O
PU
POR
B/O
PU
Pin Types
I
TO
LVDSI -Low Voltage Differential Signal Input
RSO
-Reduced Swing Differential Output
P
-Power
-Input (3.3V TTL-Compatible)
-TTL Output (3.3V TTL-Compatible)
G
PU
PD
-Ground
-Pull-Up
-Pull-Down
F
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