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參數(shù)資料
| 型號(hào)： | FPD87392BXB |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) |
| 中文描述： | 3.3 TFT - LCD的雙LVDS輸入定時(shí)控制器/雙⑩輸出區(qū)特別職務(wù)隊(duì)的TFT - LCD顯示器和筆記本電腦（SXGA / SXGA / UXGA）下 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 1980K |
| 代理商： | FPD87392BXB |
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Output Timing—TTL
Parameter
Comments
(TPW, OE2, OE1 : 3’b000)
STH Rising to Active Data
High Duration of STH
STH Rising to TP Rising
High Duration of TP
STH Rising to OE Falling
High Duration of OE
STH Rising to CPV
High Duration of CPV
STH Rising to STV
High Duration of STV
SXGA
@
54 MHz
2
1
660
54
687
189
660
422
238
1
(844)
645
1
(844)
645
1 (the first line)/2
(844/1688)
SXGA+
@
54 MHz
2
1
720
54
747
189
720
422
298
1
(844)
705
1
(844)
705
1 (the first line)/2
(844/1688)
UXGA
@
81 MHz
2
1
820
81
861
284
820
540
280
1
(1080)
805
1
(1080)
805
1 (the first line)/2
(1080/2160)
Remarks/
Unit
CLKP/N
CLKP/N
CLKP/N
CLKP/N
CLKP/N
CLKP/N
CLKP/N
CLKP/N
CLKP/N
Line
(CLKP/N)
CLKP/N
Line
(CLKP/N)
CLKP/N
Line
(CLKP/N)
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
STH Rising to REV (1 LINE)
High/Low Duration of REV (1 LINE)
t13
t14
STH Rising to REV2 (1 + 2 LINE)
High/Low Duration of REV2 (1 + 2 LINE)
Line = Hsync Cycle
TP/OE Duty Control Configuration
Resolution
TPW
OEW2
OEW1
TP
OE
(μs)
3.5
3.0
2.5
2.0
3.5
3.0
2.5
2.0
@
54 MHz
(CLK)
189
162
135
108
189
162
135
108
@
81 MHz
(CLK)
284
243
203
162
284
243
203
162
SXGA, SXGA+
@
54 MHz
UXGA
@
81 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.0 μs
54 CLK
@
54 MHz
27 CLK
@
81 MHz
0.5 μs
27 CLK
@
54 MHz
41 CLK
@
81 MHz
F
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