參數(shù)資料
型號(hào)： FPD87392
廠商： National Semiconductor Corporation
英文描述： +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA)
中文描述： 3.3 TFT - LCD的雙LVDS輸入定時(shí)控制器/雙⑩輸出區(qū)特別職務(wù)隊(duì)的TFT - LCD顯示器和筆記本電腦（SXGA / SXGA / UXGA）下
文件頁(yè)數(shù)： 7/30頁(yè)
文件大?。?/td> 1980K
代理商： FPD87392
AC Electrical Characteristics
T
A
= 0C to 70C, V
DD
= 3.0V to 3.6V, I
PI
= 100 μA (Unless otherwise specified)
LVDS Data Input
Symbol
Parameter
Conditions
Min
Max
10
Units
ms
RPLLS
RSKM
FPD-Link Receiver Phase Lock Loop Wake-up Time
RxIN Skew Margin (Note 2) and (
Figure 7
)
V
DD
= 3.3V,
CLK = 85 MHz
240
ps
Note 2:
Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window: RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type and length of cable), and source clock (FPD-Link Transmitter TxCLK IN) jitter. The specified RSKM minimum assumes a
TPPOS max of 200 ps.
RSKM = cable skew (type, length) + source clock jitter (cycle to cycle) + remaining margin for data sampling (
≥
0)
This parameter is guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (Process, Voltage, Temperature) range.
20104306
Acronyms:
RSKM
TPPOS
RSPOS
SW
Receiver Skew Margin
Transmitter Pulse Position
Receiver Strobe Position
Strobe Width
Definitions:
SW:
RSKM:
Cable Skew: Typically 10 ps 40 ps per foot.
Setup and Hold Time (Internal data sampling window)
Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + Remaining margin for data sampling (
≥
0)
FIGURE 7. FPD-Link Receiver Input Skew Margin
20104307
FIGURE 8. Ideal Strobe Position for LVDS Input
F
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