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參數(shù)資料
| 型號： | FPD87392 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) |
| 中文描述： | 3.3 TFT - LCD的雙LVDS輸入定時控制器/雙⑩輸出區(qū)特別職務(wù)隊的TFT - LCD顯示器和筆記本電腦（SXGA / SXGA / UXGA）下 |
| 文件頁數(shù)： | 10/30頁 |
| 文件大?。?/td> | 1980K |
| 代理商： | FPD87392 |
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AC Electrical Characteristics
T
A
= 0C to 70C, V
DD
= 3.0V to 3.6V, I
PI
= 100 μA (Unless otherwise specified) (Continued)
Output Timing
Symbol
RCHP
Parameter
Conditions
Min
Typ
Max
Units
RSDS Clock (RSCK) High Period
R
T
= 100
, I
PI
= 100 μA,
CLK= 85 MHz
R
T
= 100
, I
PI
= 100 μA,
CLK = 85 MHz
R
T
= 100
, I
PI
= 100 μA,
CLK = 85 MHz
R
T
= 100
, I
PI
= 100 μA,
CLK = 85 MHz
R
T
= 100
, C
L(RSDS)
= 5 pF,
I
PI
= 100 μA,
CLK = 85 MHz, RSDS[2:0] = “100”
R
T
= 100
, C
L(RSDS)
= 5 pF,
I
PI
= 100 μA, CLK= 85 MHz,
RSDS[2:0] = “100”
5.7
ns
RCLP
RSDS Clock (RSCK) Low Period
5.8
ns
SPSTU
STH Rising to RSCK Falling
3.0
ns
SPHLD
STH Falling to RSCK Falling
3.0
ns
RSTU
RS(R, G, B) Setup to Falling or
Rising Edge of RSCK
3.28
ns
RHLD
RS(R, G, B) Hold from Falling or
Rising Edge of RSCK
1.87
ns
RSDS Setup and Hold Time with Data Skew Control Values - Reference
Only
(RxCLKP/N = 85 MHz; V
= 3.0 to 3.6V, R
= 100
; I
= 100 μA; Duty Clock = 50%/50%,
±
5%; 25C)
Note: Typical values on this table are measured under Static and Steady state conditions which may not be reflective of its per-
formance in the end application.
RSDS[2:0]
Setup Time (RSTU)
Typ
1.26
1.75
2.30
2.77
3.28
3.79
4.27
4.77
Hold Time (RHLD)
Typ
3.91
3.41
2.90
2.41
1.87
1.37
0.89
0.76
Units
Min
Max
Min
Max
000
001
010
011
100
101
110
111
ns
F
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