參數(shù)資料
型號(hào)： FM33256-GTR
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO14
封裝： GREEN, MO-012AB, SOIC-14
文件頁(yè)數(shù)： 11/28頁(yè)
文件大?。?/td> 320K
代理商： FM33256-GTR
FM33256/FM3316 SPI Companion w/ FRAM
Rev. 2.0
Feb. 2009
Page 19 of 28
Command Structure
There are eight commands called op-codes that can
be issued by the bus master to the FM33xx. They are
listed in the table below. These op-codes control the
functions performed by the memory and Processor
Companion.
They
can
be
divided
into
three
categories. First, there are commands that have no
subsequent
operations.
They
perform
a
single
function, such as, enabling a write operation. Second
are commands followed by one data byte, either in or
out. They operate on the Status Register. The third
group includes commands for memory and Processor
Companion transactions followed by address and one
or more bytes of data.
Table 4. Op-code Commands
Name
Description
Op-code
WREN
Set Write Enable Latch
0000 0110b
WRDI
Write Disable
0000 0100b
RDSR
Read Status Register
0000 0101b
WRSR
Write Status Register
0000 0001b
READ
Read Memory Data
0000 0011b
WRITE
Write Memory Data
0000 0010b
RDPC
Read Proc. Companion
0001 0011b
WRPC
Write Proc. Companion
0001 0010b
WREN – Set Write Enable Latch
The FM33xx will power up with writes disabled. The
WREN command must be issued prior to any write
operation. Sending the WREN op-code will allow
the user to issue subsequent op-codes for write
operations.
These
include
writing
the
Status
Register, writing the Processor Companion, and
writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the
latch. WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit. The
WEL bit will automatically be cleared on the rising
edge of /CS following a WRDI, WRSR, WRPC, or
WRITE op-code. No other op-code affects the state
of the WEL bit. This prevents further writes to the
Status Register, F-RAM memory, or the companion
register space without another WREN command.
Figure 13 below illustrates the WREN command
bus configuration.
WRDI – Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the Status Register and verifying that WEL=0.
Figure 14 illustrates the WRDI command bus
configuration.
Hi-Z
0
1
2
3
4
5
6
7
0
1
0
CS
SCK
SI
SO
Figure 13. WREN Bus Configuration
CS
SCK
SI
SO
Hi-Z
0
1
2
3
4
5
6
7
0
1
0
Figure 14. WRDI Bus Configuration
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