參數(shù)資料
型號: FM30C256-S
廠商: Electronic Theatre Controls, Inc.
英文描述: 256Kb Data Collector
中文描述: 256Kb的數(shù)據(jù)采集器
文件頁數(shù): 12/18頁
文件大?。?/td> 260K
代理商: FM30C256-S
three bytes of a write operation to set the internal
address followed by subsequent read operations.
To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM30C256 acknowledges the address, the bus master
issues a Start condition. This simultaneously aborts
the write operation and allows the read command to
be issued with the slave address LSB set to a 1. The
operation is now a read from the current address.
Figure 10 shows the proper operation for a selective
read.
FM30C256
Rev 2.1
Dec. 2002
Page 12 of 18
RTC Write Operation
All RTC writes operate in a similar manner to
memory writes. The distinction is that a different
device ID is used and only one byte address is needed
instead of two. Figure 11 illustrates a single byte
write to the clock.
RTC Read Operation
As with writes, a read operation begins with the
Slave Address. To perform a register read, the bus
master supplies a Slave Address with the LSB set to
1. This indicates that a read operation is requested.
After receiving the complete Slave Address, the
FM30C256 will begin shifting data out from the
current register address on the next clock. Auto-
increment operates for the RTC address as with the
memory address. A current address read for the RTC
looks exactly like the memory except that the device
ID is different. The FM30C256 contains two separate
address registers, one for the 256K memory address
and the other for the RTC register address. This
allows the contents of one address register to be
modified without affecting the current address of the
other register. For example, this would allow an
interrupted read to the memory while still providing
fast access to an RTC register. A subsequent memory
read will then continue from the memory address
where it previously left off, without requiring the
load of a new memory address. However, a write
sequence always requires an address to be supplied.
S
A
Slave Address
1
Data Byte
1
P
By Master
By FM30C256
Start
Address
Stop
Acknowledge
No
Acknowledge
Data
Figure 8. Current Address Memory Read
S
A
Slave Address
1
Data Byte
1
P
By Master
By FM30C256
Start
Address
Stop
Acknowledge
No
Acknowledge
Data
Data Byte
A
Acknowledge
Figure 9. Sequential Memory Read
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