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參數(shù)資料
| 型號(hào)： | FM30C256-S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Kb Data Collector |
| 中文描述： | 256Kb的數(shù)據(jù)采集器 |
| 文件頁(yè)數(shù)： | 11/18頁(yè) |
| 文件大?。?/td> | 260K |
| 代理商： | FM30C256-S |
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be complete before the Acknowledge is sent.
Therefore, if the user desires to abort a write without
altering the memory contents, this should be done
FM30C256
Rev 2.1
Dec. 2002
Page 11 of 18
using a Start or Stop condition prior to the 8
th
data
bit. Figures 6 and 7 illustrate a single- and multiple-
writes to memory.
S
A
Slave Address
0
Address MSB
A
Data Byte
A
P
By Master
By FM30C256
Start
Address & Data
Stop
Acknowledge
Address LSB
A
Figure 6. Single Byte Memory Write
S
A
Slave Address
0
Address MSB
A
Data Byte
A
P
By Master
By FM30C256
Start
Address & Data
Stop
Acknowledge
Address LSB
A
Data Byte
A
Figure 7. Multiple Byte Memory Write
Memory Read Operation
There are two types of memory read operations. They
are current address read and selective address read. In
a current address read, the FM30C256 uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to set
the address to a specific value.
Current Address & Sequential Read
As mentioned above the FM30C256 uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving
the
complete
FM30C256 will begin shifting data out from the
current address on the next clock. The current address
is the value held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
device
address,
the
Each time the bus master acknowledges a byte,
this indicates that the FM30C256 should read
out the next sequential byte.
There are four ways to terminate a read operation.
Failing to properly terminate the read will most likely
create a bus contention as the FM30C256 attempts to
read out additional data onto the bus. The four valid
methods follow.
1.
The bus master issues a No-Acknowledge in the
9
th
clock cycle and a Stop in the 10
th
clock cycle.
This is illustrated in the diagrams below. This is
preferred.
2.
The bus master issues a No-Acknowledge in the
9
th
clock cycle and a start in the 10
th
.
3.
The bus master issues a Stop in the 9
th
clock
cycle.
4.
The bus master issues a Start in the 9
th
clock
cycle.
If the internal address reaches 7FFFh, it will wrap
around to 0000h on the next read cycle. Figures 8 and
9 show the proper operation for current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
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