參數(shù)資料
型號(hào)： FLEX6000
廠商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁(yè)數(shù)： 39/52頁(yè)
文件大?。?/td> 1811K
代理商： FLEX6000
Altera Corporation
39
FLEX 6000 Programmable Logic Device Family Data Sheet
t
OD1
t
OD2
t
OD3
t
XZ
t
ZX1
t
ZX2
t
ZX3
t
IOE
t
IN
t
IN_DELAY
Output buffer and pad delay, slow slew rate = off, V
CCIO
= V
CCINT
Output buffer and pad delay, slow slew rate = off, V
CCIO
= low voltage
Output buffer and pad delay, slow slew rate = on
Output buffer disable delay
Output buffer enable delay, slow slew rate = off, V
CCIO
= V
CCINT
Output buffer enable delay, slow slew rate = off, V
CCIO
= low voltage
IOE output buffer enable delay, slow slew rate = on
Output enable control delay
Input pad and buffer to FastTrack Interconnect delay
Input pad and buffer to FastTrack Interconnect delay with additional delay
turned on
C1 = 35 pF
(2)
C1 = 35 pF
(3)
C1 = 35 pF
(4)
C1 = 5 pF
C1 = 35 pF
(2)
C1 = 35 pF
(3)
C1 = 35 pF
(4)
t
LOCAL
t
ROW
t
COL
t
DIN_D
t
DIN_C
t
LEGLOBAL
t
LABCARRY
LAB local interconnect delay
Row interconnect routing delay
Column interconnect routing delay
Dedicated input to LE data delay
Dedicated input to LE control delay
LE output to LE control via internally-generated global signal delay
Routing delay for the carry-out of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
(5)
(5)
(5)
(5)
t
LABCASC
t
1
t
DRR
Register-to-register test pattern
Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local
interconnects
(6)
(7)
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