參數(shù)資料
型號: FLEX6000
廠商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可編程邏輯器件系列
文件頁數(shù): 30/52頁
文件大小: 1811K
代理商: FLEX6000
30
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
%
t
JCP
t
JCH
t
JCL
t
JPSU
t
JPH
t
JPCO
t
JPZX
t
JPXZ
t
JSSU
t
JSH
t
JSCO
t
JSZX
clock period
clock high time
clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock-to-output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock-to-output
Update register high impedance to valid
output
Update register valid output to high
impedance
100
50
50
20
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
25
25
20
45
35
35
t
JSXZ
35
ns
VCC
To Test
System
C1 (includes
JIG capacitance)
Device input
rise and fall
times < 3 ns
464
(703
[521
)
Device
Output
(8.06 k )
[481
250
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