參數(shù)資料
型號: FDS4935BZ
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 小信號晶體管
英文描述: Dual 30 Volt P-Channel PowerTrench MOSFET
中文描述: 6900 mA, 30 V, 2 CHANNEL, P-CHANNEL, Si, SMALL SIGNAL, MOSFET
封裝: LEAD FREE, SOP-8
文件頁數(shù): 2/5頁
文件大小: 163K
代理商: FDS4935BZ
FDS4935BZ Rev B1 (W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
'
BV
DSS
'
T
J
Coefficient
I
DSS
Zero Gate Voltage Drain Current
V
GS
= 0 V,
I
D
= –250
P
A
–30
V
Breakdown Voltage Temperature
I
D
= –250
P
A,Referenced to 25
q
C
24
mV/
q
C
V
DS
= –24 V, V
GS
= 0 V
–1
P
A
P
A
I
GSS
Gate–Body Leakage
V
GS
= +25 V, V
DS
= 0 V
+10
On Characteristics
V
GS(th)
Gate Threshold Voltage
'
V
GS(th)
'
T
J
Temperature Coefficient
r
DS(on)
Static Drain–Source
On–Resistance
(Note 2)
V
DS
= V
GS
, I
D
= –250
P
A
I
D
= –250
P
A,Referenced to 25
q
C
–1
–1.9
–3
V
Gate Threshold Voltage
–5
mV/
q
C
V
GS
= –10 V, I
D
= –6.9 A
V
GS
= –4.5 V, I
D
= –5.3 A
V
GS
= –10 V, I
D
= –6.9A,T
J
=125
q
C
V
DS
= –5 V, I
D
= –6.9 A
18
27.5
26
22
35
34
m
:
g
FS
Forward Transconductance
22
S
Dynamic Characteristics
C
iss
Input Capacitance
1360
pF
C
oss
Output Capacitance
240
pF
C
rss
Reverse Transfer Capacitance
V
DS
= –15 V, V
GS
= 0 V,
f = 1.0 MHz
200
pF
Switching Characteristics
(Note 2)
t
d(on)
Turn–On Delay Time
12
22
ns
t
r
Turn–On Rise Time
13
23
ns
t
d(off)
Turn–Off Delay Time
68
108
ns
t
f
Turn–Off Fall Time
V
DD
= –15 V, I
D
= –1 A,
V
GS
= –10 V, R
GEN
= 6
:
38
61
ns
Q
g(TOT)
Total Gate Charge, V
GS
= 10V
29
40
nC
Q
g(TOT)
Total Gate Charge, V
GS
= 5V
16
23
nC
Q
gs
Gate–Source Charge
4
nC
Q
gd
Gate–Drain Charge
V
DS
= –15 V, I
D
= –6.9 A,
V
GS
= –10 V
7
nC
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
Voltage
t
RR
Reverse Recovery Time
–2.1
A
V
SD
V
GS
= 0 V,
I
S
= –2.1 A
(Note 2)
–0.8
–1.2
V
24
ns
Q
RR
Reverse Recovery Charge
I
F
= –8.8 A,
d
iF
/d
t
= 100 A/μs
(Note 2)
9
nC
Notes:
1.
R
T
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
T
JC
is guaranteed by design while R
T
CA
is determined by the user's board design.
a) 78°C/W steady state
when mounted on a
1in
2
pad of 2 oz
copper
b) 125°C/W when
mounted on a .04 in
2
pad of 2 oz copper
c) 135°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300
P
s, Duty Cycle < 2.0%
3.
The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
F
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