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參數(shù)資料
| 型號(hào)： | FBL2041I |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 3.3V BTL 7-bit Futurebus transceiver standard A-port |
| 中文描述： | 3.3橋接7位Futurebus收發(fā)器標(biāo)準(zhǔn)A端口 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 94K |
| 代理商： | FBL2041I |
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
2
1999 Apr 27
853-2040 21374
FEATURES
7-bit BTL transceiver
Separate I/O on TTL A-port
Inverting
Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement
Drives heavily loaded backplanes with equivalent load
impedances down to 10
.
High drive 100mA BTL open collector drivers on B-port
Allows incident wave switching in heavily loaded backplane buses
Reduced BTL voltage swing produces less noise and reduces
power consumption
Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
Compatible with IEEE Futurebus+ or proprietary BTL backplanes
Controlled output ramp and multiple GND pins minimize ground
bounce
Each BTL driver has a dedicated Bus GND for a signal return
Glitch-free power up/power down operation
Low I
CC
current
Tight output skew
Supports live insertion
Pins for the optional JTAG boundary scan function are provided
High density packaging in plastic Quad Flatpack
5V compatible I/O on A-port
Industrial temperature range option available as FBL2041I
DESCRIPTION
The FBL2041/FBL2041I is a 7-bit bidirectional BTL transceiver and
is intended to provide the electrical interface to a high performance
wired-OR bus. The FBL2041 is an inverting transceiver.
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
The FBL2041/FBL2041I is pin and function compatible with FB2041
but operates at a 3.3V supply voltage, greatly reducing power
consumption.
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.
There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement. The TTL/BTL output drivers for bit 0 are enabled with
OEA1/OEB1, output drivers for bits 1–2–3 are enabled with
OEA2/OEB2 and output drivers for bits 4–5–6 are enabled with
OEA3/OEB3.
The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEAn goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEAn goes Low, A-port drivers become High impedance
without any extra delay. During power on/off cycles, the A-port
drivers are held in a High impedance state when V
CC
is below 1.3V.
The B-port has an output enable, OEB0, which affects all seven
drivers. When OEB0 is High and OEBn is Low the output driver will
be enabled. When OEB0 is Low or if OEBn is High, the B-port
drivers will be inactive and at the level of the backplane signal.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while V
CC
is Low. If live insertion is not a requirement, the
BIAS V pin should be tied to a V
CC
pin.
The LOGIC GND and BUS GND pins are isolated in the package to
minimize noise coupling between the BTL and TTL sides. These
pins should be tied to a common ground external to the package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble-shoot.
JTAG boundary scan functionality is provided as an option with
signals TMS, TCK, TDI and TDO. When this option is not present,
TMS and TCK are no-connects (no bond wires) and TDI and TDO
are shorted together internally.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
t
PLH
t
PHL
C
OB
I
OL
PARAMETER
Propagation delay
AIn to Bn
Propagation delay
Bn to AOn
Output capacitance (B0 - B6 only)
Output current (B0 - B6 only)
TYPICAL
4.2
3.5
4.8
4.9
6
100
5.2
3.2
13.5
10.7
UNIT
ns
ns
pF
mA
Standby
I
CC
Supply Current
AIn to Bn (outputs Low or High)
Bn to AOn (outputs Low)
Bn to AOn (outputs High)
mA
ORDERING INFORMATION
PACKAGE
COMMERCIAL RANGE
V
CC
= 3.3V
±
10%; T
amb
= 0 to +70
°
C
FBL2041 BB
INDUSTRIAL RANGE
V
CC
= 3.3V
±
10%; T
amb
= –40 to +85
°
C
FBL2041I BB
DWG
No.
SOT379-1
52-pin Plastic Quad Flatpack
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FBL22031BB-T | 9-Bit Bus Transceiver |
| FBL22033BB | Single 8-Bit Inverting Bus Transceiver |
| FBL22041BB-T | 7-Bit Bus Transceiver |
| FBL22031 | 9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver with 30W termination |
| FBL22031BB | 9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver with 30W termination |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FBL2041IBB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3.3V BTL 7-bit Futurebus transceiver standard A-port |
| FBL22031 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver with 30W termination |
| FBL22031BB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver with 30W termination |
| FBL22031BB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9-Bit Bus Transceiver |
| FBL22033 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3.3V BTL 8-bit latched/registered/pass-thru Futurebus universal interface transceiver |
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