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參數(shù)資料
| 型號： | FBL2031 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver |
| 中文描述： | 9位橋接3.3鎖存/注冊/直通Futurebus收發(fā)器 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 165K |
| 代理商： | FBL2031 |
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
9
AC ELECTRICAL CHARACTERISTICS
B TO A SPECIFICATIONS
T
amb
= +25
°
C,
CC
= 3.3V,
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= –40 to +85
°
C,
CC
= 3.3V
±
10%,
MIN
UNIT
MAX
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PHZ
t
PZL
t
PLZ
t
TLH
t
THL
Maximum clock frequency
Waveform 4
120
150
MHz
Propagation delay (thru mode)
Bn to An
Propagation delay (transparent latch)
Bn to An
Propagation delay
LCBA to An (latch)
Propagation delay
LCBA to An (register)
Propagation delay
SEL0 or SEL1 to An (inverting)
Propagation delay
SEL0 or SEL1 to An (non-inverting)
Output enable time from High or Low
OEA to An
Output disable time to High or Low
OEA to An
Output transition time, An Port
10% to 90%, 90% to 10%
Output to output skew for multiple
channels
1
Pulse skew
2
t
PHL
– t
PLH
MAX
Waveform 1, 2
2.8
3.0
2.8
3.4
7.7
7.5
2.7
3.0
2.9
1.9
2.0
2.8
3.0
4.0
2.6
1.4
4.3
4.5
4.9
5.0
10.2
10.1
4.2
4.5
5.8
5.8
5.9
5.6
4.4
5.6
4.0
2.6
5.9
6.0
7.0
6.6
13.0
12.9
5.7
6.1
9.1
10.4
10.3
8.8
5.7
7.3
5.4
3.7
2.2
2.6
1.8
2.8
6.1
6.1
2.1
2.4
2.2
1.2
1.4
2.2
2.6
3.2
2.1
1.0
0.2
0.1
6.8
7.3
8.4
7.8
15.6
15.4
6.7
6.9
10.5
11.6
12.3
10.0
6.6
8.3
6.0
4.4
2.0
1.2
ns
Waveform 1, 2
ns
Waveform 1, 2
ns
Waveform 1, 2
ns
Waveform 1, 2
ns
Waveform 1, 2
ns
Waveform 5, 6
ns
Waveform 5, 6
ns
Test Circuit and
Waveforms
ns
t
SK
(o)
Waveform 3
0.5
1.0
1.5
ns
t
SK
(p)
Waveform 2
0.5
1.0
1.5
ns
NOTES:
1.
t
PN
actual – t
PM
actual
for any data input to output path compared to any other data input to output path where N and M are either LH or HL.
Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.). t
SK
(0) compares t
PLH
on a given path to t
PLH
on
any other path or compares t
PHL
on a given path to t
PHL
on any other path.
2. t
SK
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FBL2031BB | 9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver |
| FBL2033 | 3.3V BTL 8-bit latched/registered/pass-thru universal transceiver |
| FBL2033BB | 3.3V BTL 8-bit latched/registered/pass-thru universal transceiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FBL2031BB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver |
| FBL2031BB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9-Bit Bus Transceiver |
| FBL2033 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3.3V BTL 8-bit latched/registered/pass-thru universal transceiver |
| FBL2033BB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3.3V BTL 8-bit latched/registered/pass-thru Futurebus universal interface transceiver |
| FBL2040 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3.3V BTL8-bit TTL to BTL transceiver |
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